Asymmetric Conductive Plugs for DRAM Overlay Margin
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Solution Overview
Problem
As semiconductor devices become more highly integrated, reducing critical dimensions of line widths makes it difficult to maintain sufficient overlay margins between conductive plugs and underlying layers during the photolithography process, limiting the fabrication of conductive plugs in advanced DRAM devices like those in 6F2 cell layouts.
Innovation Solution
A method of manufacturing semiconductor devices involves forming isolation regions, multi-layered conductive layers, and etching to create bit line and plug trenches, with conductive plug patterns that have a lower width greater than the upper width, allowing for increased contact areas and reduced electrical resistance, using layers such as doped silicon, titanium, titanium nitride, and tungsten.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If critical dimensions of line widths are reduced to increase device integration, then device integration density is improved, but overlay margins between conductive plugs and underlying layers deteriorate
Solution Approach 1:
The conductive plug is designed with asymmetric dimensions where the lower width (at the active region interface) is greater than the upper width (at the surface). This asymmetric geometry allows the broader base to provide sufficient overlay tolerance with the underlying active region, while the narrower top accommodates the reduced critical dimension requirements for high-density integration.
Solution Approach 2:
The invention changes the dimensional parameters of the conductive plug from a uniform cylinder to a tapered structure with varying cross-sectional dimensions. By allowing the lower width to be greater than the upper width, the plug maintains manufacturing tolerances at critical interfaces while enabling smaller overall dimensions for high-density device integration.
2Ease of manufacture
If conventional conductive plug formation methods are used, then manufacturing process is simple, but voids or seams form in the conductive plug
Solution Approach 1:
The conductive plug is formed as a multi-layer composite structure with different materials having different etch selectivities. The first conductive layer (e.g., tungsten) and second conductive layer (e.g., cobalt or copper) are deposited sequentially, and selective etching removes portions of these layers to form the asymmetric plug shape. This composite approach prevents void formation by ensuring complete material removal and continuous conductive pathways.
Solution Approach 2:
The conductive plug formation process is segmented into multiple sequential steps: depositing the first conductive layer, depositing the second conductive layer, selectively etching the first layer, and selectively etching the second layer. This segmentation allows precise control over the plug geometry and ensures complete filling without voids or seams at each stage.
3Reliability
If contact area of conductive plug is increased to reduce electrical resistance, then electrical conductivity is improved, but device area occupied increases
Solution Approach 1:
The asymmetric conductive plug design concentrates the contact area at the lower portion where it interfaces with the active region. The broader base provides maximum contact area with the underlying semiconductor structure to minimize resistance, while the tapered upper portion reduces the surface footprint, allowing high electrical conductivity without proportionally increasing the overall device area.
Data Source
AI summary
Methods of manufacturing a semiconductor device are provided. The method includes forming an isolation region in a substrate to define active regions extending in a single direction and being spaced apart from each other by the isolation region, forming a conductive layer in the isolation region and the active regions, etching the conductive layer to form bit line trenches extending in a first direction that is non-perpendicular to the single direction, forming bit line patterns in respective ones of the bit line trenches, etching the conductive layer to form a plurality of plug trenches two dimensionally arrayed along the first direction and a second direction perpendicular to the first direction, and filling the plug trenches with an insulation material to define conductive plug patterns in portions of the active regions. Related semiconductor devices are also provided.