Asymmetric Source-Drain Conductor Widths for Faster IC Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of integrated circuits poses challenges in design and manufacturing, leading to stricter specifications and reliability issues, particularly in signal delays and fabrication yield due to uniform terminal-conductor widths.
Innovation Solution
Adjusting the widths of terminal-conductors in integrated circuits, with some having a larger width than others, while maintaining consistent pitch distances, to reduce signal delays and improve performance without compromising fabrication yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If uniform terminal-conductor widths are used in miniaturized integrated circuits, then manufacturing consistency is maintained, but signal delays increase and performance deteriorates
Solution Approach 1:
The patent applies local quality by assigning different widths to different terminal-conductors based on their specific functional requirements. Source terminal-conductors are given larger widths to reduce resistance and improve signal speed, while drain terminal-conductors use standard widths. This localized differentiation optimizes signal performance in critical areas without uniformly increasing complexity across the entire circuit.
Solution Approach 2:
The patent implements parameter changes by modifying the width parameter of terminal-conductors from a uniform value to variable values. Specifically, source terminal-conductors are designed with widths greater than the minimum pitch distance, while drain terminal-conductors maintain the minimum pitch distance width. This parameter variation directly addresses signal delay issues by reducing resistance in source terminals where high current flow occurs.
2Speed
If terminal-conductor widths are increased to reduce resistance and improve speed, then signal performance improves, but fabrication yield may be compromised
Solution Approach 1:
The patent applies local quality by selectively increasing terminal-conductor widths only where needed for performance optimization (source terminals) rather than uniformly across all conductors. This targeted approach minimizes the impact on fabrication yield while achieving the necessary speed improvement. The source terminal-conductors use widths greater than the minimum pitch distance, while other conductors maintain standard dimensions.
Solution Approach 2:
The patent implements controlled parameter changes by modifying the width parameter of specific terminal-conductors (source terminals) to be greater than the minimum pitch distance, while maintaining the minimum pitch distance for drain terminal-conductors and other standard conductors. This selective parameter adjustment optimizes speed performance without excessively complicating the manufacturing process.
3Loss of time
If non-uniform terminal-conductor widths are implemented, then signal delays are reduced and performance improves, but design complexity increases
Solution Approach 1:
The patent applies local quality by implementing non-uniform widths only for source terminal-conductors while maintaining uniform widths for drain terminal-conductors and other standard conductors. This localized differentiation reduces signal delays in critical paths without requiring complex non-uniform designs throughout the entire circuit, thereby limiting the increase in design complexity to only the necessary areas.
Solution Approach 2:
The patent implements targeted parameter changes by modifying the width parameter of source terminal-conductors to be greater than the minimum pitch distance, while keeping drain terminal-conductors at the minimum pitch distance width. This selective parameter adjustment reduces signal delays in source terminals without requiring comprehensive redesign of all conductors, thus limiting the increase in overall design complexity.
Data Source
AI summary
A device includes: first and second power rails; first and second active regions; a first source/drain (S/D) conductor, wherein: the first S/D conductor is conductively connected to the first active region and the first power rail, and is in a layer between the first active region and the first power rail; a second S/D conductor, wherein: the second S/D conductor is at a same level as the first S/D conductor, the second S/D conductor is conductively connected to the first active region and is spaced apart from the first power rail, and the first S/D conductor is wider than the second S/D conductor; and a first gate between the first S/D conductor and the second S/D conductor, wherein: the first gate, the first S/D conductor, and the second S/D conductor are components of a first transistor at the first active region.