Asymmetric Source-Drain Contact Layout for Lower RC Delay
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Solution Overview
Problem
The reduction of resistance-capacitance (RC) delay in interconnects of integrated circuits (ICs) is hindered by increasing contact resistances and capacitances, which limits further scaling down of ICs and negates performance improvements, particularly in advanced technology nodes.
Innovation Solution
A dynamic metal-to-device (MD) width and poly pitch layout design is proposed, which reduces resistance at the device source-side and capacitance at the device drain-side by adjusting the width and pitch of metal-to-drain/source contacts, thereby decreasing RC delay and improving IC device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If geometry size is reduced to achieve faster operating speeds, then signal travel distance is reduced, but resistance-capacitance delay increases and negates performance improvements
Solution Approach 1:
The patent applies local quality by differentiating the treatment of source and drain contacts. The source contact is designed with larger dimensions (wider width and/or longer length) to minimize resistance, while the drain contact is optimized for minimal capacitance to the gate. This localized optimization of contact properties addresses the RC delay problem by treating different regions of the device differently based on their specific electrical requirements.
2Reliability
If contact dimensions are increased to reduce resistance, then resistance decreases, but capacitance increases
Solution Approach 1:
The source contact is designed with larger dimensions (wider width and/or longer length) to minimize resistance, while the drain contact is optimized for minimal capacitance to the gate. This localized optimization of contact properties addresses the RC delay problem by treating different regions of the device differently based on their specific electrical requirements.
Solution Approach 2:
The patent introduces asymmetry in the contact design by making the source contact dimensions (width and/or length) different from the drain contact dimensions. Specifically, the source contact is made larger to reduce resistance, while the drain contact is made smaller to reduce capacitance. This asymmetric design breaks the symmetry of conventional equal-sized contacts and optimizes the RC delay by addressing the different electrical requirements of source and drain.
3Ease of manufacture
If symmetric contact design is used for source and drain, then manufacturing is simplified, but RC delay cannot be optimized
Solution Approach 1:
The patent introduces asymmetry in the contact design by making the source contact dimensions (width and/or length) different from the drain contact dimensions. Specifically, the source contact is made larger to reduce resistance, while the drain contact is made smaller to reduce capacitance. This asymmetric design breaks the symmetry of conventional equal-sized contacts and optimizes the RC delay by addressing the different electrical requirements of source and drain.
Data Source
AI summary
Provided are a semiconductor device and a method of forming the same. The semiconductor device includes: at least one gate structure having a first side and a second side opposite to each other; a first source/drain (S/D) feature disposed at the first side of the at least one gate structure; a second S/D feature disposed at the second side of the at least one gate structure; a first metal-to-drain/source (MD) contact disposed on the first S/D feature; and a second MD contact disposed on the second S/D feature, wherein a contact area between the first MD contact and the first S/D feature is greater than a contact area between the second MD contact and the second S/D feature.