Asymmetric Double Diffused Drain Junctions for Leakage Control
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Solution Overview
Problem
Conventional self-boosting methods in NAND-type flash memory devices suffer from leakage currents and soft programming due to hot carriers, particularly affecting memory cell transistors adjacent to the ground selection transistor, leading to reduced programming efficiency.
Innovation Solution
The implementation of asymmetrically positioned second impurity regions with varying depths between selection gates and memory cell gates, along with additional selection gates, to reduce leakage currents and prevent soft programming by controlling the channel voltage and boosting levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional self-boosting method is used to prevent non-selected cell transistors from being programmed, then programming selectivity is improved, but leakage current and hot carrier-induced soft programming occur in junction regions
Solution Approach 1:
The patent applies different impurity concentrations at different locations: higher concentration in the ground selection transistor source/drain regions and lower concentration in the memory cell transistor source/drain regions. This local differentiation suppresses leakage current and hot carrier effects specifically in the ground selection transistor without affecting the programming operation of memory cell transistors, thereby resolving the contradiction between programming selectivity and harmful leakage currents.
Solution Approach 2:
The patent changes the impurity concentration parameter in the source/drain regions of the ground selection transistor to be higher than that in memory cell transistors. This parameter modification increases the threshold voltage and reduces the channel voltage in the ground selection transistor, preventing hot carrier injection and soft programming while maintaining programming selectivity through proper voltage application during programming operations.
2Manufacturing precision
If program inhibition voltage is applied to non-selected bit lines to prevent soft programming, then programming accuracy is improved, but leakage current increases in junction regions between selection transistors and memory cell transistors
Solution Approach 1:
The patent implements local quality differentiation by doping the ground selection transistor source/drain regions with higher impurity concentration than memory cell transistor source/drain regions. This creates a localized high-field region that suppresses band-to-band tunneling and leakage current specifically where needed, allowing program inhibition voltage to be applied without causing harmful leakage effects in the junction regions.
3Reliability
If higher impurity concentration is used in source/drain regions to reduce leakage current, then reliability is improved, but manufacturing complexity increases due to multiple doping steps
Solution Approach 1:
The patent segments the doping process into two distinct steps: first doping the entire active region to a base concentration, then selectively re-doping the ground selection transistor source/drain regions to higher concentration. This segmentation allows precise control of impurity distribution through selective masking, achieving the desired reliability improvement while managing manufacturing complexity through systematic process division.
Solution Approach 2:
The patent performs preliminary doping of the entire active region to a base impurity concentration before subsequent selective re-doping. This preliminary action establishes a uniform foundation that simplifies the second doping step, as only specific regions need additional impurity concentration adjustment. The preliminary doping ensures all regions have minimum required concentration while the second step creates the differentiated high-concentration zones where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes leakage currents and hot carrier-induced soft programming, stabilizes the boosting level, and enhances programming efficiency by maintaining shallow source/drain junctions and employing a double diffused drain structure.
Implementation Method 1
a gate induced drain leakage current (GIDL) and/or a band-to-band tunneling (BTBT) may be generated in the junction regions
Implementation Method 2
A program voltage Vpgm may be applied to a selected word line such that electrons may be injected into the selected cell transistor by Fowler-Nordheim (FN) tunneling
Data Source
AI summary
A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.