Asymmetric Dual Gate Transistor for Back Bias Control
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Solution Overview
Problem
Conventional field-effect transistors (FETs) with back bias capability suffer from high parasitic capacitance due to large overlap between the back gate and the transistor structure, which affects performance and efficiency.
Innovation Solution
The design of an asymmetric dual gate fully depleted transistor with two gates of dissimilar lengths, where one gate controls the state and operation, and the other modulates the threshold voltage, reducing parasitic capacitance and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a back gate is added to provide back bias capability, then bias control is improved, but parasitic capacitance increases due to large overlap between the back gate and transistor structure
Solution Approach 1:
The patent employs asymmetric gate structures where the first gate and second gate have different lengths. The first gate extends over the channel region while the second gate has a reduced length that minimizes overlap with the source and drain regions. This asymmetric design provides back bias capability through the second gate while reducing parasitic capacitance by limiting the overlap area between the back gate structure and the transistor components.
Solution Approach 2:
The gate structure is segmented into two distinct gates with different functions. The first gate primarily controls the channel, while the second gate provides back bias capability. This segmentation allows independent optimization of each gate's length and position, enabling back bias functionality while minimizing parasitic capacitance through careful design of the second gate's reduced length.
2Ease of operation
If gate length is increased to improve control, then control capability is improved, but parasitic capacitance increases due to larger overlap area
Solution Approach 1:
The patent uses asymmetric gate lengths where the first gate is longer to provide strong control over the channel, while the second gate is shorter to minimize parasitic capacitance. This asymmetric configuration allows the control gate to have sufficient length for effective control, while the back bias gate maintains adequate control capability with reduced length to limit overlap and capacitance.
Data Source
AI summary
Techniques that facilitate an asymmetric dual gate fully depleted transistor are provided. In one example, a transistor device includes a semiconductor channel structure, a first gate structure and a second gate structure. The first gate structure comprises a first length. The second gate structure comprises a second length that is different than the first length. The first gate structure is disposed on a first surface of the semiconductor channel structure and the second gate structure is disposed on a second surface of the semiconductor channel structure.