Transistor TRIZ Cases

Simultaneous implantation of varied cations reduces processing time and cost while maintaining precise doping profiles.

Differentiated gate insulating film thicknesses reduce random noise and white blemishes in amplification transistors formed by ion implantation.

A semiconductor diode uses a curved impurity concentration profile to stabilize electrical conductivity.

Alternating semiconductor switch parts reduce thermal stress from inrush currents in capacitive loads.

A solid-state image sensor limits charge retention in the floating diffusion unit to suppress pseudo-smear artifacts.

Thickens semiconductor landing areas via silicide reaction to prevent void formation and improve contact reliability in nanometer-scale thin film layers.

A current breaker uses a resistive film to sense voltage across the switching element for precise overcurrent protection.

A GaN HEMT gate circuit uses a series depletion-mode transistor to dynamically limit input current.

A semiconductor device uses a trench structure with a floating gate opposed to the side surface of the trench.

Aluminum nitride buried layers in silicon-on-insulator substrates mitigate self-heating in CMOS devices while maintaining electrical insulation.

A dynamic random access memory structure uses bit line trenches with contacts on both sidewalls to connect adjacent vertical transistors.

Inclined active regions intersect word and bit lines to increase DRAM cell density within a fixed chip area.

Connecting the light blocking film to the source electrode prevents leakage current while maintaining thin film transistor signal response.

Self-aligned fin cut formation relaxes lithography misalignment constraints, enhancing process window and fabrication efficiency.

Sequential voltage application protects devices from short-circuits while minimizing conduction losses in power converters.

A pixel unit uses a connection unit to selectively route signals from first and second pixel groups to a shared vertical signal line.

Orientation engineering shapes epitaxial growth on fin sidewalls to enhance carrier mobility while reducing integration defects.

Sidewall spacer formation reduces photolithographic complexity by defining distinct dopant profiles through selective etching and ion implantation.

An adhesive layer bonds the conductive cover and insulating layers on a semiconductor memory capacitor structure.

Silicon free wheel diodes provide negative temperature characteristics that reduce forward voltage and prevent positive feedback loops during inrush currents.

A buried gate semiconductor device uses a nitride film spacer to prevent short-circuiting between isolation regions.

A buried n-type region lowers the threshold voltage of a Pch MOSFET body layer while maintaining high impurity concentration elsewhere.

An asymmetric dual gate fully depleted transistor uses dissimilar gate lengths to modulate threshold voltage and control channel operation.

Mandrel-based self-alignment prevents electrical shorting between adjacent vias and gate contacts during aggressive semiconductor scaling.

High doping concentration in the source and drain regions reduces contact resistance while selective heating minimizes interface defects.

Insulating plugs isolate lateral faces in a double-gate transistor, preventing wedge effects that degrade carrier mobility.

An integrated circuit uses a floating node and clamp circuits to provide electrostatic discharge protection while powered.

A semiconductor fin structure uses a separator insulating layer to form self-aligned contacts between gate electrodes and source/drain regions.

Adjusting raised source and drain layer heights maintains consistent electric current across transistors with varying active region widths.

Parallel supports contact capacitor lower electrode walls to maintain vertical alignment during semiconductor memory fabrication.

Grating light shielding defines poly-silicon zones with distinct grain sizes, enabling single-step ion doping to reduce leakage current and manufacturing cost.

This CMOS structure replaces poly-silicon gates with composite metal layers to eliminate boron penetration and depletion effects that reduce gate capacitance and driving force.

A surrounded gate electrode structure reduces parasitic capacitance in oxide semiconductor transistors.

A slanted polyhedral recess in the substrate enlarges the contact area between the conductive structure and the active region.

One-time top-contact trench etching merges gate and source body contact formation to reduce geometrical tolerances and simplify manufacturing.

Sidewall trench spacers position floating gates vertically, resolving substrate area constraints while enabling ballistic injection programming efficiency.

Graded silicon content in three passivation layers suppresses leakage currents, stabilizing gate-off voltage and preventing color distortion.

A gate electrode protrusion extends along the boundary between the gate contact and capping pattern to increase the physical contact area.

A bi-directional transient voltage suppressor uses an NPN bipolar transistor with segmented base doping to optimize junction breakdown characteristics.

Segmenting the source and drain into lightly doped and highly doped epitaxial layers conserves stress near the channel to mitigate short channel effects.

Setting the free wheel diode mesa width above 0.3 micrometers stabilizes characteristics and reduces on-resistance despite miniaturization.

Silicide block material forms gate, source, and drain regions to suppress surface states, reducing low-frequency noise while maintaining high-voltage stability.

A semiconductor bonding pad overlaps the circuit element to reduce chip area while a high-modulus metal film disperses stress.

A thermal insulating layer and metal film act as an etch stop during heater section fabrication to define the thermal actuator element structure.

A buried conductive field shield reduces peak electric fields in high voltage laterally diffused MOSFET drift regions.

A driver circuit adjusts pull-down resistance to manage gate capacitance discharge current.

Engineered oxide layers trap interface defects to reduce current leakage in scaled non-planar semiconductor devices.

A floating gate nonvolatile memory device uses a contact plug as a control gate to eliminate separate fabrication steps and improve integration.