FinFET Fin Cut Self-Alignment via Selective Etching
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Solution Overview
Problem
Existing FinFET devices and fabrication methods lack flexibility in forming fin cuts, leading to process constraints such as misalignment and overlay issues during lithography and etching processes.
Innovation Solution
A method for fabricating FinFET devices that involves forming fin cuts with a self-alignment nature, using selective etching processes to relax these constraints and improve process control, by removing exposed portions of fin features and forming isolation features in trenches, allowing for more precise and flexible integration of high-k/metal gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography and etching processes are used to form fin cuts, then fin features can be created, but misalignment and overlay issues occur reducing manufacturing precision
Solution Approach 1:
The fin cut formation process utilizes self-alignment where the fin cut is automatically positioned relative to the gate structure through the etch process itself, eliminating the need for separate lithography alignment steps. The etch process naturally aligns the fin cut with the gate trench, providing self-service positioning that avoids misalignment issues.
Solution Approach 2:
The gate trench is formed first as a preliminary structure that serves as a reference for subsequent fin cut formation. By establishing the gate trench position beforehand, the fin cut can be precisely positioned relative to it through self-aligned etching, preventing overlay issues that would occur with sequential lithography steps.
2Productivity
If existing FinFET fabrication methods are used, then devices can be manufactured, but process window is limited reducing productivity
Solution Approach 1:
The self-aligned fin cut formation process automatically compensates for process variations through the etch mechanism itself, providing inherent process control without requiring tight parameter control in separate lithography and etching steps. This self-regulating mechanism expands the process window and improves both productivity and reliability.
3Ease of manufacture
If multiple separate processes are used for fin cut formation, then fin features can be created, but process complexity increases making manufacturing difficult
Solution Approach 1:
The fin cut formation is merged with the gate trench etch process into a single self-aligned operation. Instead of using separate lithography and etching steps to define fin cuts, the method combines these functions into one etch process that simultaneously creates the gate trench and positions fin cuts, simplifying the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances process simplicity, improves process window, and relaxes constraints like misalignment and etch profile control, resulting in more efficient and precise FinFET device fabrication.
Implementation Method 1
using selective etching processes to relax these constraints and improve process control, by removing exposed portions of fin features
Data Source
AI summary
A semiconductor device includes a semiconductor substrate; an isolation region over the semiconductor substrate; and two fin features over the semiconductor substrate and protruding above the isolation region. The two fin features are generally aligned along their longitudinal direction. The device further includes two gate structures disposed over a top surface of the isolation region and engaging top surface and sidewalls of the two fin features respectively. The device further includes source and drain features disposed over the fin features and on both sides of each of the gate structures. The device further includes a first structure disposed between and protruding above the fin features, wherein a bottom surface of the first structure is below the top surface of the isolation region.