FinFET Orientation Engineering for Mobility and Junction Sharpness
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Solution Overview
Problem
Conventional finFET manufacturing methods face challenges with diamond shape epitaxial semiconductor material causing integration issues, server defects, and worse electron mobility, particularly when using (100) wafers, which affect transistor performance metrics like on-resistance versus drain-induced barrier lowering (Ron-DIBL).
Innovation Solution
The method involves forming fin structures with (100) sidewalls using a silicon-containing semiconductor substrate, converting some to germanium-containing types, and forming N-type and P-type epitaxial semiconductor materials with rectangular growth on source and drain portions to enhance mobility and reduce defects, employing orientation engineering for CMOS FinFET integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If diamond shape epitaxial semiconductor material is used in conventional finFET manufacturing, then the manufacturing process can be completed, but integration issues occur, server defects increase, and electron mobility deteriorates
Solution Approach 1:
The patent changes the crystal orientation parameter of the fin structure from conventional orientations to (100) sidewalls, which fundamentally alters the epitaxial growth morphology from diamond shape to rectangular shape. This parameter change resolves the integration issues and defects while maintaining manufacturing feasibility.
Solution Approach 2:
The patent employs selective germanium incorporation in silicon-germanium (SiGe) fin structures combined with silicon nitride stressors and specific epitaxial materials. This composite material approach enhances electron mobility while achieving rectangular epitaxial growth, simultaneously improving reliability and ease of manufacture.
2Ease of manufacture
If conventional fin orientations are used, then manufacturing is straightforward, but electron mobility is reduced and Ron-DIBL performance deteriorates
Solution Approach 1:
The patent changes the crystal orientation parameter to (100) sidewalls and introduces selective germanium incorporation, which transforms the epitaxial growth from diamond to rectangular shape. This enables superior electron mobility and Ron-DIBL performance while maintaining manufacturing feasibility through standardized processes.
Solution Approach 2:
The patent applies local quality by incorporating germanium selectively in specific fin structures (SiGe fins) rather than uniformly across all fins. This localized material modification optimizes electron mobility in nFET regions while maintaining compatibility with pFET regions, resolving the performance contradiction.
3Reliability
If rectangular epitaxial growth is formed on (100) sidewalls with selective germanium incorporation, then electron and hole mobility increase and junction sharpness improves, but process complexity increases
Solution Approach 1:
The patent changes the fin orientation parameter to (100) sidewalls, which naturally produces rectangular epitaxial growth morphology. This parameter change simplifies the overall process by eliminating the need for complex mask patterns or post-growth shaping, despite the specialized orientation requirement.
Solution Approach 2:
The patent performs preliminary action by forming the (100) oriented fin structures and selective SiGe regions before epitaxial growth. This preliminary structuring enables the subsequent rectangular epitaxial growth to occur naturally without additional processing steps, reducing overall process complexity while achieving superior mobility and junction characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases electron and hole mobility, achieves sharper junctions, and provides a more robust epitaxial growth process, improving transistor performance by reducing defects and enhancing Ron-DIBL, thus improving overall device performance.
Implementation Method 1
N-type epitaxial semiconductor material having rectangular growth is formed on the source and drain portions of the sidewalls having the (100) plane of the fin structures that are germanium free, and P-type epitaxial semiconductor material having rectangular growth is formed on the source and drain portions of the sidewalls having the (100) plane of the germanium containing type fin structures.
Data Source
AI summary
A semiconductor device that includes at least one germanium containing fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.