Bi-layer Embedded Stressor FETs for Short Channel Control
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Solution Overview
Problem
Current semiconductor technologies face challenges in achieving a balance between stressor proximity and short channel effects in embedded stressor processes, with existing methods either leading to poor short channel control or compatibility issues with advanced gate stacks.
Innovation Solution
A bi-layer embedded epitaxy semiconductor source and drain region is introduced, comprising an undoped or lightly doped first epitaxy material that induces strain and a highly doped second epitaxy material for superior dopant activation and short channel control, eliminating the need for traditional deep and heavily doped regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a late embedded stressor process is used to form in-situ doped stressor material after extension formation, then stress conservation and lower source/drain resistance are achieved, but short channel effects are degraded due to deep and heavily doped source and drain regions
Solution Approach 1:
The source/drain region is segmented into multiple epitaxial layers with different doping concentrations. The first epitaxial layer has lower doping concentration to maintain short channel control, while the second epitaxial layer has higher doping concentration to provide stress conservation and low resistance, eliminating the need for a single deep heavily doped region
Solution Approach 2:
Different regions of the source/drain structure are assigned different doping concentrations tailored to their specific functions: the first epitaxial layer (lower doping) is optimized for short channel control near the channel, while the second epitaxial layer (higher doping) is optimized for stress conservation and resistance reduction
2Stress or pressure
If an early embedded stressor process is used to form undoped epitaxy stressor material prior to extension ion implantation, then stress proximity to the device channel is improved, but stress relaxation occurs and the process requires complicated first spacers with compatibility issues with high k/metal gate stacks
Solution Approach 1:
The first epitaxial layer is formed preliminarily before extension formation to provide stress proximity to the channel, but unlike the early embedded stressor process, it uses in-situ doped material that maintains stress without relaxation and avoids the need for complicated first spacers and their associated compatibility issues
3Reliability
If traditional deep and heavily doped source and drain regions are used, then high dopant activation is achieved, but strain conservation is degraded and short channel control is worsened
Solution Approach 1:
The doped region is segmented into two epitaxial layers where the second epitaxial layer provides high dopant activation for low resistance while the first epitaxial layer maintains appropriate doping levels to preserve strain conservation and short channel control, eliminating the need for a single deep heavily doped region
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances strain conservation and short-channel control, reducing external resistance while maintaining performance without degrading short channel effects.
Implementation Method 1
A first epitaxy semiconductor material that induces a strain upon a channel of the at least one gate stack. The first epitaxy semiconductor material has a lattice constant that is different from a lattice constant of the semiconductor substrate
Implementation Method 2
A second epitaxy semiconductor material located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material
Data Source
AI summary
A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack, e.g., FET, located on an upper surface of a semiconductor substrate. The structure further includes a first epitaxy semiconductor material that induces a strain upon a channel of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.