Vertical Transistor DRAM With Dual-Sidewall Bit Line Contacts
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Solution Overview
Problem
The existing methods for forming buried bit lines in dynamic random access memory (DRAM) with vertical transistor structures are complex and result in a poor process window due to the need for multiple anisotropic etching steps and difficulty in controlling the size and location of single sidewall contacts.
Innovation Solution
A method involving the formation of bit line trenches with two bit lines, each connected to adjacent transistors via contacts on both sidewalls, and the use of a conductive layer divided into two portions to create separated bit lines, reducing the complexity of the etching process and improving contact control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single sidewall contact is formed in a trench surrounded by insulation liner layer, then the bit line can be electrically connected to the channel region, but the process becomes very complicated and results in a poor process window
Solution Approach 1:
The patent divides the single complex sidewall contact formation into multiple simpler contact formations on different surfaces. Specifically, contacts are formed on the bottom surface and both sidewalls of the trench separately, which simplifies the etching process and improves the process window while maintaining reliable electrical connection
Solution Approach 2:
The patent transitions from forming a contact on a single sidewall surface to forming contacts on multiple surfaces (bottom and both sidewalls) of the trench. This dimensional expansion from one surface to three surfaces simplifies the overall process by allowing standard etching techniques to be applied to multiple faces rather than requiring complex single-sidewall selective etching
2Manufacturing precision
If multiple anisotropic etching steps are used to form single sidewall contacts, then the bit line connection can be achieved, but the process window deteriorates
Solution Approach 1:
The patent segments the contact formation process into multiple independent contact formations on different surfaces (bottom contact and sidewall contacts). This segmentation allows each contact to be formed with standard etching processes, avoiding the need for multiple complex anisotropic etching steps and thereby improving the process window
Solution Approach 2:
The patent uses the trench structure itself as a mold or template to automatically define the position and shape of multiple contacts. By forming contacts on the bottom and sidewalls of the same trench, the process benefits from self-alignment, improving manufacturing precision without requiring additional complex etching steps
Data Source
AI summary
The present invention provides a dynamic random access memory (DRAM) including a plurality of transistors formed in a semiconductor substrate, wherein each of the transistors includes a vertical channel region. A plurality of bit line contained trenches is formed in the semiconductor substrate. Each of the bit line contained trenches comprises two bit lines, and each of the bit lines is electrically connected to an adjacent transistor. Each two sidewalls of each of the bit line contained trenches have a contact formed thereon. A plurality of word lines are formed over the plurality of bit lines and electrical connect to the plurality of transistors. Furthermore, a method for fabricating the DRAM is also provided.