Double-Gate Transistor With Insulated Lateral Faces

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Solution Overview

Problem

The presence of a completely encapsulating gate in transistors with semiconducting bars can degrade performance by affecting carrier mobility and electrostatic control, particularly for certain bar dimensions and materials, due to wedge effects and different crystallographic orientations.

Innovation Solution

A double-gate transistor structure is implemented with semiconducting bars where the gate electrode is distributed on top and bottom faces, and lateral faces are electrically insulated using plugs, allowing conduction only on surfaces with the same crystallographic orientation, similar to 'plane' transistor structures, and incorporating a semiconducting material with a different lattice parameter to strain the bars and improve electrical performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a completely encapsulating gate is used to improve electrostatic control of the channel, then electrostatic control is improved, but carrier mobility and output current performance are degraded due to wedge effects and different crystallographic orientations

Engineering Contradiction:

Improveelectrostatic controlVSAvoidcarrier mobility degradation

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The gate structure is segmented into two separate gates: a first gate facing the top face of the semiconducting bar and a second gate facing the bottom face. This segmentation eliminates the need for a completely encapsulating gate, preventing wedge effects and crystallographic orientation issues at lateral faces while maintaining electrostatic control through the dual-gate configuration

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Insulating plugs are introduced as intermediary elements that fill spaces between the gates and the lateral faces of the semiconducting bar. These plugs prevent direct contact between the gate and lateral faces with different crystallographic orientations, eliminating the harmful wedge effects while allowing the gates to maintain electrostatic control over the channel

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If a completely encapsulating gate is used to improve electrostatic control, then electrostatic control is improved, but wedge effects at lateral faces degrade the electrostatic control

Engineering Contradiction:

Improveelectrostatic controlVSAvoidelectrostatic control degradation

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The gate structure is divided into two separate gates positioned at the top and bottom, avoiding the need for lateral gate extension that causes wedge effects. This segmentation simplifies the electrostatic control mechanism by eliminating the complex interactions at lateral faces

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Insulating plugs serve as mediators that prevent the formation of wedge effects by blocking direct gate-lateral face contact. These plugs simplify the electrostatic control by eliminating the complex field distributions that arise from lateral gate-bar interfaces

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances carrier mobility and electrostatic control by preventing electrostatic interference at lateral faces, improving output current performance and maintaining defect-free epitaxial growth, while allowing strain addition in the transport plane.

Implementation Method 1

lateral faces of the semiconducting bars are electrically insulated from the gate by means of insulation plugs that extend in contact with the lateral faces of the semiconducting bars

Methodology Applied

Scientific EffectElectrical insulation: Dielectric

Implementation Method 2

a given (third) semiconducting material with a lattice parameter different from the second semiconducting material can be grown on the upper face and the lower face of the second bars... The given material that is grown is advantageously configured so as to strain the semiconducting bars forming at least a channel region

Methodology Applied

Scientific EffectStrain: Deformation

Implementation Method 3

Epitaxial growth is facilitated by the fact that it is only done on the same type of crystalline plane... A given (third) semiconducting material with a lattice parameter different from the second semiconducting material can be grown on the upper face and the lower face of the second bars

Methodology Applied

Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS11177371B2Transistor with superposed bars and double-gate structure

Publication Date: 2021.11.16 COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

AI summary

A method is provided for fabricating a double gate structure for transistors with superposed bars, including: providing, on a support, a stack including an alternation of one or several first bars based on a first semiconducting material, and one or several second bars based on a second semiconducting material; removing lateral portions of the second bars; forming insulating plugs in contact with lateral regions of the second bars; removing the first bars; and forming a gate electrode facing an upper face and a lower face of the second bars, the insulating plugs being arranged in contact with the lateral regions of the second bars when the gate electrode is being formed.