Raised Source and Drain Layers for Transistor Current Matching
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Solution Overview
Problem
The performance of semiconductor devices is compromised due to the narrowing of active regions during the oxidation process in the manufacturing of field effect transistors, leading to reduced electric current and performance degradation, especially in transistors with different breakdown voltage types.
Innovation Solution
The solution involves forming field effect transistors with raised source and drain layers of varying heights on active regions of different widths, using selective epitaxial growth with dichlorosilane and hydrogen chloride, to maintain consistent electric current and reduce resistance variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an oxidation process (thermal treatment process) is carried out in the manufacturing process of a semiconductor device, then the gate insulating film can be formed, but the width of the active region becomes narrower than the design value due to edge oxidation
Solution Approach 1:
The patent applies local quality by forming raised source and drain layers with different heights on different active regions. Specifically, first raised source and drain layers are formed with a first height on first active regions, while second raised source and drain layers are formed with a second height on second active regions. This local differentiation compensates for the oxidation-induced width reduction, maintaining consistent electric current characteristics across devices with varying active region widths.
Solution Approach 2:
The patent changes the height parameter of the raised source and drain layers to compensate for active region width variations. By adjusting the height of the raised layers based on the active region width, the invention maintains consistent electric current characteristics despite oxidation process effects on different sized active regions.
2Reliability
If the width of the active region is reduced by oxidation, then the device isolation is improved, but the electric current of the field effect transistor is lowered
Solution Approach 1:
The patent implements local quality by differentiating the height of raised source and drain layers according to the specific active region width. First raised source and drain layers with a first height are formed on first active regions, while second raised source and drain layers with a second height are formed on second active regions, locally compensating for oxidation effects and maintaining consistent electric current.
Solution Approach 2:
The patent addresses the width reduction problem by moving to another dimension - the vertical height dimension. Instead of trying to maintain the original horizontal width, the invention compensates by increasing the vertical height of the raised source and drain layers, thereby maintaining the cross-sectional area and electric current characteristics.
3Ease of manufacture
If selective epitaxial growth is used to form raised layers, then the source and drain regions can be formed, but additional manufacturing steps are required
Solution Approach 1:
The patent applies local quality through selective epitaxial growth, forming raised source and drain layers with different heights on different active regions. This localized formation approach enables precise control over the vertical dimensions of source and drain regions, compensating for oxidation-induced width variations and maintaining consistent device characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses performance degradation by adjusting the height of the raised layers in response to active region size deviations caused by thermal treatment, thereby maintaining consistent electric current and improving transistor reliability.
Implementation Method 1
a process of simultaneously forming the first raised source layer, the first raised drain layer, the second raised source layer and the second raised drain layer is provided by using selective epitaxial growth
Implementation Method 2
an oxidation process (thermal treatment process) carried out in a manufacturing process of a semiconductor device
Implementation Method 3
an oxidation process (thermal treatment process) carried out in a manufacturing process of a semiconductor device
Data Source
AI summary
To suppress performance degradation of a semiconductor device, when the width of a first active region having a first field effect transistor formed therein is smaller than the width of a second active region having a second field effect transistor formed therein, the height of a surface of a first raised source layer of the first field effect transistor is made larger than the height of a surface of a second raised source layer of the second field effect transistor. Moreover, the height of a first surface of a raised drain layer of the first field effect transistor is made larger than a surface of a second raised drain layer of the second field effect transistor.