Trench Spacer Floating Gates for Flash Memory Density
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Solution Overview
Problem
Current non-volatile flash memory technologies face challenges in efficiently using substrate area for memory cells, particularly in NOR and NAND arrays, where floating gates are often positioned on the substrate surface, limiting storage density and requiring complex voltage management for programming and erasing.
Innovation Solution
The formation of floating gate charge storage element memory cells using trenches with spacers along sidewalls, allowing for conductive control gates and select transistors in substrate surface areas, enabling efficient use of substrate area and optimized programming through ballistic injection, while avoiding the need for complex voltage management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If floating gates are positioned on the substrate surface, then memory cell structure is simple, but substrate area usage is inefficient and storage density is limited
Solution Approach 1:
The patent transitions from planar floating gate positioning on the substrate surface to three-dimensional positioning within substrate trenches. The floating gates are formed along the sidewalls of trenches etched into the substrate, utilizing the vertical dimension to increase storage density while maintaining efficient substrate area usage. This dimensional change allows multiple memory cells to be stacked vertically rather than occupying horizontal space.
Solution Approach 2:
The patent embeds floating gates within substrate trenches, nesting the charge storage elements inside the substrate structure rather than placing them on the surface. The trenches act as containers that hold the floating gates, tunnel dielectric layers, and control gates in a compact vertical arrangement, effectively nesting multiple functional layers within the substrate volume.
2Device complexity
If complex voltage management is used for programming and erasing, then memory cell functionality is complete, but device complexity increases
Solution Approach 1:
The patent extracts the voltage management complexity from the memory cell operation by utilizing ballistic injection mechanisms that rely on simple electric field formation rather than complex multi-step voltage sequencing. The trench structure naturally confines electric fields, simplifying the voltage requirements for programming and erasing operations while maintaining complete memory cell functionality.
Solution Approach 2:
The patent changes the operational parameters of the memory cell by employing ballistic injection, which requires different voltage conditions compared to conventional tunneling methods. The trench structure enables efficient electron acceleration with simplified voltage waveforms, changing the electrical parameters needed for programming and erasing while reducing overall system complexity.
3Quantity of substance
If floating gates are formed using conventional methods, then manufacturing process is established, but storage density is limited
Solution Approach 1:
The patent forms floating gates in three dimensions within substrate trenches using sequential deposition and etching processes. Material layers are deposited conformally on trench sidewalls, then selectively etched to create floating gate structures that extend vertically along the trench walls. This three-dimensional formation method increases the effective floating gate surface area and storage density while using established semiconductor manufacturing techniques.
Solution Approach 2:
The patent segments the floating gate formation process into multiple discrete steps: trench formation, conformal dielectric deposition, floating gate material deposition, and selective etching. This segmentation allows precise control over floating gate dimensions and positioning within the trenches, enabling high storage density while maintaining manufacturability through standardized process modules.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces substrate surface area usage, enhances storage density, and improves programming efficiency by allowing direct electron acceleration onto floating gates, minimizing interference and increasing the capacity of memory cells.
Implementation Method 1
floating gate charge storage element memory cells are formed with the use of trenches or cavities in which the floating gates are positioned along sidewalls
Implementation Method 2
enabling efficient use of substrate area and optimized programming through ballistic injection, while avoiding the need for complex voltage management
Data Source
AI summary
In order to reduce the integrated circuit area that is occupied by an array of a given number of flash memory cells, floating gate charge storage elements are positioned along sidewalls of substrate trenches, preferably being formed of doped polysilicon spacers. An array of dual floating gate memory cells includes cells with this structure, as an example. A NAND array of memory cells is another example of an application of this cell structure. The memory cell and array structures have wide application to various specific NOR and NAND memory cell array architectures.