Slanted Contact Recess for Semiconductor Memory Devices
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Solution Overview
Problem
As semiconductor devices integrate more densely, the reduction in insulation interlayer thickness and contact area between conductive structures leads to increased electric resistance and potential electrical shorts, causing operation failures in devices like DRAM and flash memory.
Innovation Solution
A semiconductor memory device with a contact structure featuring a slanted bottom portion on the substrate, forming a multi-faced polyhedral recess to increase the contact area between the contact structure and the active region, using a wet etching process with alkaline etchants to create slanted sidewalls without damaging the insulation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the contact area between contact structure and conductive structure is reduced to increase integration density, then device integration degree is improved, but contact resistance increases causing operation failures
Solution Approach 1:
The contact structure transitions from a conventional planar geometry to a three-dimensional slanted configuration. The bottom surface of the contact structure is formed with slanted surfaces at specific angles (e.g., 45 degrees) relative to the substrate, creating additional contact area in the vertical dimension while maintaining a compact footprint in the horizontal plane. This dimensional transformation allows increased integration density without compromising contact resistance.
Solution Approach 2:
The invention modifies the geometric parameters of the contact structure by introducing slanted surfaces with specific angle parameters. The slant angle (e.g., 45 degrees) and the extent of the slanted portion are controlled to optimize the balance between contact area and device footprint. This parameter adjustment enables smaller gap distances between conductive structures while maintaining adequate contact area for low resistance.
2Productivity
If the insulation interlayer thickness is reduced to increase integration density, then device integration degree is improved, but electrical short between conductive structures occurs
Solution Approach 1:
The contact structure utilizes a slanted three-dimensional configuration that extends vertically into the insulation interlayer. This vertical extension allows the contact structure to reach through thinner insulation layers without requiring increased horizontal spacing, thereby maintaining electrical isolation while achieving high integration density.
Solution Approach 2:
The contact structure employs asymmetric geometry with slanted surfaces at specific angles rather than symmetric vertical walls. This asymmetric design allows the contact structure to navigate through the insulation interlayer more effectively, creating adequate clearance from adjacent conductive structures and preventing electrical shorts even when the insulation layer thickness is reduced.
3Ease of manufacture
If the contact structure uses conventional vertical geometry, then manufacturing is simple, but contact area is insufficient leading to high contact resistance
Solution Approach 1:
The slanted bottom surface of the contact structure is formed during the initial contact hole etching process using pre-defined mask patterns and etch conditions. By establishing the slanted geometry in advance during the patterning and etching steps, the structure is prepared for subsequent filling operations without requiring additional complex processing steps, thus maintaining manufacturing simplicity while achieving increased contact area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces contact resistance and mitigates operation failures by enlarging the contact area, even when gap distances and line widths are minimized due to high integration density.
Implementation Method 1
using a wet etching process with alkaline etchants to create slanted sidewalls without damaging the insulation layer
Data Source
AI summary
In a semiconductor device having an enlarged contact area between a contact structure and a substrate, the substrate may include a first region on which a conductive structure is arranged and a second region defining the first region. The first region may include a multi-faced polyhedral recess of which at least one of the sidewalls is slanted with respect to a surface of the substrate. An insulation layer may be formed on the substrate to a thickness that is sufficient to cover the conductive structure. The insulation layer has a contact hole that may be communicated with the recess. The active region of the substrate is exposed through the contact hole. A conductive pattern is positioned in the recess and the contact hole. Accordingly, the contact resistance at the active region of the substrate may be kept to a relatively low value even though the gap distances and line width of pattern lines are reduced.