Self-aligned via formation for semiconductor bridging prevention
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Solution Overview
Problem
As semiconductor technology nodes shrink, bridging problems occur where components intended to be electrically isolated unintentionally short together, posing challenges in fabrication and device performance, and existing techniques like overlay control are not sufficient to prevent these issues.
Innovation Solution
A novel fabrication process flow that self-aligns components to prevent bridging by forming self-aligned vias over conductive contacts, using a unique etching and deposition process to create openings that laterally cover both contacts, ensuring that conductive material filling these openings does not bridge adjacent vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used, then manufacturing process is simple, but bridging occurs between adjacent vias causing electrical shorting
Solution Approach 1:
The patent performs preliminary actions by forming mandrels and dielectric layers before via etching, creating a self-aligned structure that prevents bridging. The mandrels are formed first, then dielectric material is deposited over them, and finally vias are etched through the dielectric to expose the mandrels, ensuring precise alignment before the actual via formation occurs.
Solution Approach 2:
The patent introduces mandrels as intermediary structures that facilitate precise via placement. These mandrels serve as temporary placeholders that define the exact positions where vias should be formed, acting as a mediator between the dielectric layer and the final via structure, ensuring that vias are correctly positioned without direct alignment between etch steps.
2Productivity
If device scaling continues, then functional density increases, but bridging risk increases between components
Solution Approach 1:
The patent segments the via formation process into distinct steps: forming mandrels, depositing dielectric material, etching vias through the dielectric to expose mandrels, and removing mandrels. This segmentation allows each step to be optimized independently, ensuring precise via placement even as device dimensions scale down and functional density increases.
Solution Approach 2:
The patent performs preliminary actions by forming mandrels and dielectric layers before via etching, creating a self-aligned structure that prevents bridging. The mandrels are formed first, then dielectric material is deposited over them, and finally vias are etched through the dielectric to expose the mandrels, ensuring precise alignment before the actual via formation occurs.
3Reliability
If overlay control is used to prevent bridging, then manufacturing complexity increases, but bridging prevention is insufficient
Solution Approach 1:
The patent employs self-aligned via formation where the structure itself guides the via placement. The mandrels and dielectric layers are configured so that when vias are etched, they automatically align with the underlying features without requiring complex overlay control. The process uses the deposited material's own geometry to define via positions, making the system self-correcting and eliminating the need for additional alignment controls.
Solution Approach 2:
The patent introduces mandrels as intermediary structures that facilitate precise via placement. These mandrels serve as temporary placeholders that define the exact positions where vias should be formed, acting as a mediator between the dielectric layer and the final via structure, ensuring that vias are correctly positioned without direct alignment between etch steps.
Data Source
AI summary
First and second gates and first and second conductive contacts are disposed over a substrate. First and second vias are disposed over the first and second conductive contacts, respectively. A first gate contact is disposed over the first gate. A dielectric structure is disposed over the first gate and over the second gate. A first portion of the dielectric structure is disposed between the first and second vias. A second portion of the dielectric structure is disposed between the first via and the first gate contact. A first interface between the first conductive contact and the first via constitutes a first percentage of an upper surface area of the first conductive contact. A second interface between the first gate and the first gate contact constitutes a second percentage of an upper surface area of the first gate. The first percentage is greater than the second percentage.