Driver Circuit Gate Capacitance Discharge Control
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Solution Overview
Problem
Conventional driver circuits face issues with excessive gate capacitance discharge current leading to breakdown of PMOSFETs when operating across a wide range of high voltage power supply voltages, particularly at lower voltage levels, due to inadequate resistance value switching in the pull-down resistor circuit.
Innovation Solution
A driver circuit with a resistor switching circuit that adjusts the resistance value of the variable resistance circuit based on the high voltage power supply voltage level, switching to a higher resistance value when the voltage is low to suppress discharge current and prevent voltage exceeding the breakdown voltage, and a lower resistance value when the voltage is high to ensure proper operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional driver circuit with fixed resistance value is used, then the circuit structure is simple, but the gate capacitance discharge current becomes excessive at low voltage levels causing PMOSFET breakdown
Solution Approach 1:
The patent applies dynamics by making the resistance value changeable based on operating conditions. Specifically, the pull-down resistor is switched between a first resistance value (for low voltage operation) and a second resistance value (for high voltage operation) according to the power supply voltage level, allowing the circuit to adapt to different operating conditions and prevent PMOSFET breakdown while maintaining simplicity.
Solution Approach 2:
The patent changes the resistance parameter of the pull-down resistor based on the power supply voltage level. When the power supply voltage is low, a first resistance value is used to limit discharge current; when the power supply voltage is high, a second resistance value is used. This parameter change prevents PMOSFET breakdown at low voltages while ensuring proper operation at high voltages.
2Reliability
If the resistance value is increased to suppress discharge current, then PMOSFET breakdown is prevented, but the discharge speed becomes too slow at high voltage levels
Solution Approach 1:
The patent makes the resistance value dynamic by switching between two different values based on the power supply voltage level. At low voltage levels, a higher first resistance value suppresses discharge current to prevent breakdown. At high voltage levels, a lower second resistance value enables fast discharge. This dynamic adjustment resolves the contradiction between reliability and speed.
Solution Approach 2:
The resistance parameter is changed based on operating conditions: a first resistance value is used when power supply voltage is low to limit current and prevent breakdown, while a second resistance value is used when power supply voltage is high to enable rapid discharge. This parameter adaptation simultaneously achieves both reliable voltage control and adequate discharge speed.
3Adaptability or versatility
If a single resistance value is used for all voltage levels, then the circuit is simple, but proper operation cannot be maintained across a wide range of power supply voltages
Solution Approach 1:
The patent applies dynamics by implementing a resistance switching mechanism that adapts the pull-down resistor value to the power supply voltage level. The circuit switches between a first resistance value and a second resistance value based on voltage thresholds, enabling proper operation across a wide voltage range while maintaining relatively simple circuit structure through the use of switching transistors.
Solution Approach 2:
The resistance parameter is adaptively changed according to the power supply voltage level. When the voltage is low, a first resistance value ensures safe operation by limiting discharge current. When the voltage is high, a second resistance value maintains proper functionality. This parameter adaptation enables wide voltage range operation with controlled complexity.
Data Source
AI summary
A driver circuit includes a gate capacitance discharge circuit that reduces a resistance value of a resistor for pulling down the gate of a PMOSFET at the output stage for a predetermined period at the timing when an NMOSFET turns on and a pull-down resistor switching circuit that switches pull-down resistors of the gate capacitance discharge circuit, based on a divided voltage into which voltage of the high voltage power supply system is divided, in which the pull-down resistor switching circuit, when the divided voltage is higher than a reference voltage Vref, switches the pull-down resistor for the predetermined period to a resistor and, when the divided voltage is the reference voltage Vref or lower, switches the pull-down resistor to a resistor having a higher resistance value than the resistor.