CMOS Dual Metal Gate Work Function Tuning
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Solution Overview
Problem
Conventional poly-silicon gates in semiconductor devices face performance issues due to boron penetration and depletion effects, leading to reduced gate capacitance and driving force, prompting the need for improved work function metals in CMOS devices with complex dual metal gate processes.
Innovation Solution
A CMOS device with a PMOS having a P-type metal gate comprising a bottom barrier layer, P work function metal layer, N work function tuning layer, and N work function metal layer, and an NMOS with an N-type metal gate including an N work function tuning layer and low-resistance metal layer, where the bottom barrier and P work function metal layers are selectively removed and replaced to optimize electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional poly-silicon gate is used, then manufacturing process is simple, but device performance deteriorates due to boron penetration and depletion effect
Solution Approach 1:
The patent changes the material parameter of the gate electrode from poly-silicon to metal materials with different work functions. By selecting specific metals (e.g., tungsten, titanium nitride, tantalum nitride) and controlling their thickness and composition, the gate achieves optimal electrical characteristics without boron penetration issues, thereby improving device performance while maintaining manufacturability through established PVD/CVD processes
Solution Approach 2:
The patent employs composite gate structures combining multiple metal layers with different functions. For example, a bottom barrier layer (e.g., titanium nitride) prevents diffusion, a middle work function layer (e.g., tungsten) provides electrical characteristics, and a top protective layer ensures stability. This multi-layer composite approach solves both performance and manufacturing challenges
2Reliability
If dual metal gate method is used to replace poly-silicon gate, then device performance improves, but manufacturing process complexity increases
Solution Approach 1:
The patent divides the gate structure into functionally distinct segments: a bottom barrier layer for diffusion prevention, a middle work function layer for electrical control, and a top protective layer for stability. This segmentation allows each layer to be optimized independently while simplifying the overall manufacturing process through standardized deposition sequences
Solution Approach 2:
The patent develops a universal gate structure that can serve both NMOS and PMOS devices with minor material adjustments. By using a common bottom barrier layer and protective layer design, and only varying the middle work function layer material or thickness, the same manufacturing process framework can produce both transistor types, reducing process complexity
3Reliability
If work function metals are used to replace poly-silicon gates, then gate capacitance and driving force improve, but material thickness and composition control become more critical
Solution Approach 1:
The patent incorporates a bottom barrier layer before the work function metal layer to pre-establish diffusion barriers and adhesion promoters. This preliminary action prevents subsequent material degradation and reduces sensitivity to thickness variations in the work function layer, thereby maintaining electrical performance without requiring extremely tight thickness control
Solution Approach 2:
The patent applies different material compositions and thicknesses at different gate locations to optimize local electrical characteristics. For example, the work function layer thickness may be varied across the gate width or length to compensate for local electric field variations, while the bottom barrier layer provides uniform protection throughout. This localized optimization maintains performance while allowing broader process windows
Data Source
AI summary
The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.