Buried Gate Semiconductor Device with Nitride Spacer
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Solution Overview
Problem
As semiconductor memory devices shrink in size, they face issues such as short channel effects, increased parasitic capacitance, and Gate Induced Drain Leakage (GIDL) due to reduced design rules and increased impurity doping, leading to deteriorated refresh characteristics and operational reliability.
Innovation Solution
A semiconductor device with a buried gate region and a nitride film spacer formed over the sidewalls of the buried gate region, where the spacer is etched to remain in the device isolation region, preventing short-circuiting and inter-cell leakage by filling voids caused by poor gap-filling characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length of the transistor is decreased to reduce unit cell size, then the data storage capacity increases, but short channel effects and DIBL occur leading to deteriorated operational reliability
Solution Approach 1:
The patent introduces a three-dimensional channel structure where the channel extends in the vertical direction (z-axis) in addition to the horizontal direction. This dimensional change allows the channel length to be maintained vertically even as the horizontal channel width is reduced, thereby preserving operational reliability while enabling smaller unit cell sizes for increased storage capacity.
2Productivity
If the distance between word line and bit line is reduced to increase integration degree, then the device density increases, but parasitic capacitance is increased deteriorating sense amplifier operation margin
Solution Approach 1:
The patent introduces a buried gate structure that acts as an intermediary element between the word line and bit line. This buried gate, formed in a recess and covered with insulation film, provides electrical isolation that reduces parasitic capacitance between adjacent lines, allowing closer spacing for higher integration while maintaining adequate operation margins for the sense amplifier.
3Reliability
If a buried gate structure is formed to reduce parasitic capacitance, then the parasitic capacitance between bit line and word line is reduced, but Gate Induced Drain Leakage occurs between conductive material and N-type junction
Solution Approach 1:
The patent applies different material properties and structural characteristics to different regions: the buried gate uses conductive material for capacitance reduction, while the insulation film covering it provides electrical isolation. The spacer regions use different etching characteristics to maintain proper spacing. This local differentiation of material qualities allows the buried gate to reduce parasitic capacitance while preventing GIDL through proper insulation and spacing.
4Reliability
If a nitride film spacer is formed over sidewalls of the buried gate region and etched to remain in the device isolation region, then short-circuiting between device isolation region and neighboring gates is prevented, but the device complexity increases
Solution Approach 1:
The nitride film spacer is formed preliminarily over the sidewalls of the buried gate region before final etching. This preliminary formation creates a protective layer that prevents short-circuiting between the device isolation region and neighboring gates during subsequent processing steps. The selective etching that removes the spacer from active regions while retaining it in isolation regions is a planned preliminary protective measure.
Data Source
AI summary
A semiconductor device and a method for manufacturing the same are disclosed, in which a buried gate region is formed, a nitride film spacer is formed at sidewalls of the buried gate region, and the spacer is etched in an active region in such a manner that the spacer remains in a device isolation region. Thus, if a void occurs in the device isolation region, the spacer can prevent a short-circuit from occurring between the device isolation region and its neighboring gates.