GaN HEMT Gate Current Limiting Circuit with Dynamic FET Switch
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Solution Overview
Problem
Conventional GaAs and GaN HEMTs face challenges in effectively limiting gate current during input-side overload, leading to increased negative gate voltages and reduced transistor robustness, especially at high input powers.
Innovation Solution
A circuit arrangement using a first FET and a DC voltage supply network with a high-resistance resistor and a second FET in series, where the second FET switches off in depletion mode based on the gate current, creating a variable resistor that limits the current independently of input power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a high-resistance resistor is used in the gate supply network to limit gate current, then gate current is reduced, but the transistor operates in deep Class C mode with increased negative gate voltages
Solution Approach 1:
A second FET is introduced as an intermediary device between the gate and the high-resistance resistor. This second FET acts as a controlled switch that can be turned off by the voltage drop across the resistor, thereby mediating the relationship between current limiting and voltage generation. When the second FET is off, it prevents the formation of deep negative gate voltages while still allowing the resistor to limit gate current effectively.
2Object-affected harmful factors
If conventional limiting switches (diodes, Zener diodes) are used at the input, then gate current is limited, but the component cannot be monolithically integrated requiring a second chip
Solution Approach 1:
The limiting function previously requiring separate diode components is merged into the existing FET structure by utilizing the second FET's gate terminal and its inherent switching characteristics. This integration eliminates the need for external limiting switches and additional chips, reducing device complexity while maintaining the gate current limiting function.
3Object-affected harmful factors
If high-resistance resistor is used to limit gate current, then some current reduction is achieved, but gate current continues to increase with increasing input power
Solution Approach 1:
The circuit transitions from a static resistance-based limiting approach to a dynamic switching approach. The second FET's state changes dynamically based on the voltage drop across the resistor, creating a feedback mechanism that adapts the limiting strength to the actual gate current conditions. This dynamic response ensures effective current limiting across varying input power levels.
Solution Approach 2:
The voltage drop across the high-resistance resistor provides feedback control for the second FET's gate voltage. When gate current increases, the voltage drop increases, which turns off the second FET, thereby preventing further current increase. This feedback mechanism ensures that gate current is effectively limited regardless of input power variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively reduces gate current by up to 20-fold at high input powers without affecting small-signal behavior or noise figure, allowing for robust and compact LNAs with faster recovery times.
Implementation Method 1
the second FET switches off in depletion mode based on the gate current, creating a variable resistor that limits the current independently of input power
Data Source
Figure 1~2
Figure 3~4
Figure 5a~5d
AI summary
The invention relates to a circuit assembly for limiting the gate current at a field-effect transistor, in particular a circuit assembly for limiting the gate current at a GaN or HaAs HF power HEMT in an analogue amplifier circuit. A circuit assembly according to the invention for limiting the gate current at a field-effect transistor (FET) comprises a first FET (10) and a DC voltage supply network (20) connected to a gate connection (12) of the first FET (10), wherein the supply network (20) provides a voltage Vgg to the gate connection (12) of the first FET (10) via a first connection (22), having a high-ohmic resistor R1 (220) and a series-connected second FET (222) with a gate connection (224), wherein the second FET (222) is in an ON state when a gate source voltage is 0 V and said gate connection (224) is also connected to the gate connection (12) of the first FET (10) in parallel with the resistor R1 (220) via a second connection (24), wherein a voltage drop occurring at the resistor R1 (220) leads to an increasing blocking of the second FET (222).