Strained Material Stack for FinFET Contact Resistance Reduction
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Solution Overview
Problem
The challenge in semiconductor integrated circuit manufacturing is to achieve enhanced performance of field effect transistors (FETs) while scaling down their dimensions, which requires reducing contact resistance (Rcsd) in FinFETs by lowering the Schottky barrier height and increasing doping density.
Innovation Solution
The solution involves a contact structure and method that includes high strain and high doping concentration in source and drain regions, with a dopant segregation design, band alignment tuning, and selective local high-temperature heating to reduce interface defects, achieved through a strained material stack and metal-silicide formation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FET dimensions are scaled down to increase functional density, then production efficiency increases and costs decrease, but contact resistance increases and performance deteriorates
Solution Approach 1:
The patent applies parameter changes by modifying the doping concentration and strain characteristics of the semiconductor layers. Specifically, it uses high doping concentration (e.g., 1E19 to 1E21 atoms/cm³) and high strain (>1%) in the source/drain regions to reduce contact resistance. This resolves the contradiction by changing material parameters rather than geometric dimensions, allowing continued scaling while maintaining electrical performance.
Solution Approach 2:
The patent employs composite materials through the strained material stack consisting of multiple layers with different compositions (e.g., SiGe, SiC, Si). These composite structures provide both mechanical strain to enhance carrier mobility and appropriate band alignment to reduce Schottky barrier height, thereby reducing contact resistance without increasing device dimensions.
2Area of moving object
If FET dimensions are scaled down, then functional density increases, but Schottky barrier height increases making contact resistance reduction difficult
Solution Approach 1:
The patent changes the band alignment parameters by introducing strained material stacks with specific compositions. The strain modifies the band structure to reduce Schottky barrier height at the metal-semiconductor interface, counteracting the increase in barrier height that normally occurs with device scaling.
Solution Approach 2:
The patent applies local quality by creating high doping concentration regions specifically at the contact interfaces where metal contacts are formed. This localized doping (e.g., 1E19 to 1E21 atoms/cm³) reduces contact resistance at critical interfaces without affecting the overall device dimensions or channel characteristics.
3Reliability
If doping density is increased to reduce contact resistance, then carrier mobility improves, but interface defects increase
Solution Approach 1:
The patent uses composite strained material stacks (e.g., SiGe/Si/SiC layers) that provide strain-induced carrier mobility enhancement while the specific material composition and interface structure minimize defect formation. The strain reduces effective mass and enhances mobility without the high doping concentrations that would create excessive interface defects.
Solution Approach 2:
The patent optimizes the strain parameter (>1%) and doping concentration (1E19 to 1E21 atoms/cm³) to achieve the right balance. The strain provides mobility enhancement through band structure modification, while controlled doping at these specific levels reduces contact resistance without creating excessive interface defects that would occur at much higher doping levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contact resistance by lowering the Schottky barrier height and increasing doping density, improving the performance of FinFETs by enhancing carrier mobility and reducing interface defects.
Implementation Method 1
high strain and high doping concentration in source and drain regions
Implementation Method 2
selective local high-temperature heating to reduce interface defects
Implementation Method 3
metal-silicide formation process
Data Source
AI summary
An embodiment is a method of manufacturing a semiconductor device, the method including forming a first gate over a substrate, forming a recess in the substrate adjacent the first gate, epitaxially forming a strained material stack in the recess, the strained material stack comprising at least three layers, each of the at least three layers comprising a dopant. The method further includes co-implanting the strained material stack with dopants comprising boron, germanium, indium, tin, or a combination thereof, forming a metal layer on the strained material stack, and annealing the metal layer and the strained material stack forming a metal-silicide layer.