Strained Semiconductor Layer for Data Retention in Memory Devices
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Solution Overview
Problem
The performance of semiconductor memory devices is limited by the probability of electron tunneling through barriers, which affects data retention and reliability, particularly in non-volatile memory technologies like flash memory and SONOS memories.
Innovation Solution
The use of strained semiconductor layers, specifically strained silicon on insulator (SSOI) structures and a contact etch stop layer (CESL) or dual contact etch stop layer (DCESL), combined with low temperature plasma oxidation processes, reduces the tunneling probability by increasing the barrier height and effective electron conductivity mass, thereby enhancing data retention and endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor structures are used, then manufacturing is simpler, but electron tunneling probability is high leading to poor data retention
Solution Approach 1:
The patent applies strain engineering by introducing tensile strain to the silicon substrate through various methods (epitaxial growth, substrate curvature, stressor layers) to modify the electronic band structure. This changes the effective mass and mobility of charge carriers, thereby reducing electron tunneling probability and improving data retention without fundamentally changing the memory device architecture
Solution Approach 2:
The patent employs composite material structures including strained silicon-on-insulator (SOI) layers combined with nitride-based floating gates and oxide barriers. The combination of strained Si, SiO2, and Si3N4 layers creates a multi-layer composite structure that leverages the beneficial properties of each material to reduce tunneling while maintaining manufacturability
2Reliability
If higher barrier heights are used to reduce tunneling, then data retention improves, but manufacturing precision requirements increase
Solution Approach 1:
Instead of increasing barrier thickness, the patent changes the physical state of the silicon substrate by introducing strain. This modifies the electronic properties (effective mass, mobility) to reduce tunneling probability, achieving improved data retention without requiring tighter control on oxide layer thickness
3Reliability
If low temperature plasma oxidation is used, then thermal budget is reduced improving data retention, but oxidation rate decreases
Solution Approach 1:
The patent utilizes plasma phase to conduct oxidation at lower temperatures. The plasma state enables reactive oxygen species to oxidize silicon at reduced thermal budgets, improving data retention by preventing thermal degradation while maintaining acceptable oxidation rates through enhanced chemical reactivity in the plasma phase
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces electron tunneling currents and improves data retention and reliability in semiconductor memory devices, particularly in nitride-based memories, by creating deeper traps and altering the electron conductivity mass, leading to better performance and radiation hardness.
Implementation Method 1
The underlying physical mechanism which contributes to a better performance of a strained semiconductor substrate is a reduction of the probability that an electron tunnels through barriers provided within a semiconductor structure. The height of the tunnel oxide barrier may be increased by the use of tensile stress strained substrates. The strain would reduce tunnel leakage currents by increasing the barrier height between a SiO2 layer and a Si layer via strain-induced changes in the Si and SiO2 electron affinity.
Implementation Method 2
fabrication of certain oxide layers of the memory device by a low temperature plasma oxidation process may further improve the data retention characteristics of the memory device through a reduction of thermal budget
Data Source
AI summary
A semiconductor memory device comprising a strained semiconductor layer and a contact etch stop layer, CESL, wherein the strained semiconductor layer and the CESL are both arranged to reduce the probability of an electron tunnelling out of a charge trapping layer of the semiconductor memory device.