Asymmetric Electrode Semiconductor Data Storage Pattern
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices, such as phase change random access memory (PRAM) and resistive random access memory (RRAM), face challenges in increasing the degree of integration of memory devices due to limitations in three-dimensionally arranged memory cells, leading to scattering of cell characteristics and inconsistent memory operation.
Innovation Solution
A semiconductor device design featuring a first and second conductive line arrangement on a substrate with a data storage structure and selector structure in series, where the data storage structure includes a lower data storage electrode, data storage pattern, and upper data storage electrode, with specific geometric configurations to enhance integration and symmetry, reducing cell characteristic scattering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensionally arranged memory cells are used to increase integration, then the degree of integration is improved, but cell characteristic scattering increases and memory operation consistency deteriorates
Solution Approach 1:
The patent applies asymmetry by intentionally designing the data storage pattern with non-uniform electrode positioning. Specifically, the first and second electrodes are positioned at different distances from the data storage pattern, creating an asymmetric configuration that compensates for process variations and reduces cell characteristic scattering in three-dimensionally arranged memory cells
Solution Approach 2:
The patent implements local quality by varying the electrode positions relative to the data storage pattern based on local requirements. The first electrode is positioned closer to the data storage pattern than the second electrode, creating localized field distributions that optimize memory operation consistency across different regions of the three-dimensional structure
Data Source
AI summary
A semiconductor device including a data storage pattern is provided. The semiconductor device includes a first conductive line disposed on a substrate and extending in a first direction, a second conductive line disposed on the first conductive line and extending in a second direction, and a first data storage structure and a first selector structure disposed between the first conductive line and the second conductive line and connected in series. The first data storage structure includes a first lower data storage electrode, a first data storage pattern, and a first upper data storage electrode. The first lower data storage electrode includes a first portion facing the first upper data storage electrode and vertically aligned with the first upper data storage electrode. The first data storage pattern includes a first side surface and a second side surface facing each other. The first upper data storage electrode and the first portion of the first lower data storage electrode are disposed to be closer to the first side surface of the first data storage pattern than to the second side surface of the first data storage pattern.