Solid-State Devices TRIZ Cases

Branch wiring on the terminal face serves as a reference line to confirm chamfer quantities and prevent outer lead bonding pad peeling.

An octagonal storage electrode design reduces occupied area in thin film transistor arrays to increase the aperture ratio.

Segmenting the second electrode with an insulating barrier reduces dark spots and maintains low resistance despite foreign material risks.

A semiconductor layer with a narrower central width reduces off-current flow paths while preserving side surface area for electron transport.

A memory device uses interleaved bit lines and floating voltages to reduce inter-bit line capacitance.

Replacing transmissive materials with a reflective layer in the pixel defining structure prevents lateral light leakage and improves color purity.

A single poly-silicon non-volatile memory structure enables direct integration with standard CMOS logic processes.

Segmenting the spacer into a metal post and cored solder ball reduces connection pad pitch while maintaining substrate distance.

An auxiliary electrode merges with the gate or drain layer to lower second electrode resistance in OLED displays.

Ink-jet printed color filters and laser ablated black matrices integrate on a single substrate to simplify manufacturing.

Stepped electrode structures in a 3D semiconductor device reduce dummy region area to increase memory cell density without raising manufacturing complexity.

Crystalline organic semiconductor layers overcome amorphous material limitations by enabling efficient charge carrier transport and extended diffusion lengths.

An asymmetric electrode design reduces cell characteristic scattering in three-dimensional memory structures, improving operation consistency.

Laminated organic photoelectric conversion layers using specific semiconductor materials enhance hole mobility and absorption coefficients.

Formula 1 and Formula 2 materials in the emission layer balance hole and electron transport, resolving device complexity constraints.

Control circuit applies higher voltage to selection lines to induce Gate Induced Drain Leakage for efficient erase voltage delivery.

Applying substrate bias voltage during deposition to control phase change material stoichiometry, reducing chalcogen content for consistent PCRAM switching.

Composite organic insulators with tuned dielectric constants lower operating and threshold voltages while maintaining chemical stability.

Automated die selection pairs matched semiconductor components to reduce lot-to-lot variations and improve manufacturing efficiency.

Doping a chalcogenide layer with carbon and nitrogen increases crystallization temperature to improve data retention without raising set resistance.

A metal silicide layer coats the pipe connection gate electrode to lower electrical resistance in 3D nonvolatile memory structures.

Patsnap Eureka analyzes a CMOS image sensor microlens method using openings to prevent bridge formation during thermal flow.

A first oxide semiconductor layer protects the buffer layer in thin film transistors.

A non-volatile memory cell design positions a second capacitive implant region outside the gate structure to maintain stable channel dimensions.

Auxiliary etch stopper prevents pin hole faults in oxide thin film transistors caused by gate insulation and passivation layer etch depth differences.

A transistor stress layer incorporates a barrier ion doped region to support a low resistivity electrical contact layer formed via salicide processing.

Parallel grooves diffuse high-intensity overhead LED light into the light guide unit, resolving thickness and uniformity trade-offs.

Transfer printing an ink streak portion forms source and drain electrodes, enabling sub-5 μm channel lengths for high-speed integrated circuits.

Variable resistance memory cells generate Joule heat through segmented lower electrodes and sacrificial pattern etching for precise material placement.

A single-crystal germanium layer forms on an insulating substrate through rapid thermal annealing and liquid phase epitaxy.

Laser radiation creates modified layers near semiconductor elements to suppress chipping progression from interfaces during dicing.

Drain-select-level isolation structures segment vertical semiconductor channels to enhance electrical isolation in three-dimensional memory arrays.

Segmenting the substrate isolates capacitive electrodes from the display area, preventing static breakdown while enabling circuit testing.

An epitaxial vertical semiconductor channel maintains high on-current despite increased channel length from higher word line levels in 3D NAND memory.

Secondary electrodes extract diffusing plasma to prevent contamination of adjacent switches in the array.

Direct contact between the spacer and overcoat layer increases adhesive force, preventing detachment during assembly.

A wavelength conversion layer fills a reflective cavity to cover a light-emitting device while exposing an electrode.

Tetradentate platinum compounds enable saturated color emission in full-color displays without complex filter layers.

Coplanar light shielding layers block backside light incidence in solid state imaging devices while maintaining electrical connectivity.

Decreasing grating intervals from center to edge expand the longitudinal viewing space and reduce crosstalk interference in naked eye 3D displays.

Two-axis positioning and rotatable optics align MRAM dies to the laser beam, maintaining signal-to-noise ratios across the wafer.

A secondary current source in the driver circuit allows the optocoupler to differentiate between logical low signals and power failure conditions.

Vertical wordline straps and dummy bitcells merge metal contacts to shrink active bitcell areas while improving electrical conductivity.

Nano-particles self-assemble in recesses to reduce electrode contact area, limiting peak current and resolving bit-to-bit non-uniformity.

A semiconductor IGBT uses segmented collector contacts to distribute current and minority carrier implantation across active regions.

Gallium oxide controlling layer balances electron and hole transport to extend device lifespan.

A sacrificial layer enables laser-induced cracking to remove encapsulation material from display pad areas without additional masks.

A single patterning process forms interlayer dielectric, source, drain, and pixel electrode patterns on an OLED array substrate.

Using identical materials for emission and carrier transport layers eliminates interface energy barriers, reducing driving voltage.

Luminescence-assisting layers stabilize the emission region and prevent exciton deactivation, maintaining color consistency.