Transistor Stress Layer Barrier Ion Doping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing transistors with stress layers have limited improvement in carrier mobility and leakage current suppression due to lattice mismatch and diffusion issues, leading to increased contact resistance and reduced performance.
Innovation Solution
A barrier layer is formed in the stress layer by doping barrier ions, preventing metal atoms from diffusing to the bottom of the stress layer, and an electrical contact layer with a first metal element of lower resistivity is created using a salicide process, ensuring low resistance and uniform thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stress layer is formed in the source region and drain region to improve carrier mobility, then the drive current is increased, but the metal atoms diffuse to the bottom of the stress layer causing contact resistance increase
Solution Approach 1:
A barrier layer is introduced as an intermediary between the metal layer and the stress layer. This barrier layer prevents metal atoms from diffusing into the stress layer while allowing the stress layer to maintain its carrier mobility enhancement function. The barrier layer acts as a mediator that blocks the harmful diffusion path without interfering with the beneficial stress effect on carrier mobility.
Solution Approach 2:
The structure is segmented into distinct layers: a barrier layer is separated from the stress layer to create a clear interface that prevents atom diffusion. This segmentation isolates the metal atoms in the upper layer from reaching the bottom of the stress layer, thereby preventing contact resistance increase while preserving the stress-induced carrier mobility improvement.
2Productivity
If the gate size is reduced to increase component density, then the integration degree is improved, but short-channel effect occurs causing leakage current
Solution Approach 1:
The stress layer modifies the physical parameters of the channel region by introducing mechanical stress through lattice mismatch. This stress alters the carrier transport properties, improving carrier mobility and enabling better control of the channel even at reduced gate sizes. The parameter change in stress state compensates for the reduced gate control capability.
Solution Approach 2:
The stress layer uses composite material structures (such as SiGe or SiC layers) with different lattice constants than silicon. These composite materials generate controlled stress in the channel region through lattice mismatch, enhancing carrier mobility and helping to suppress leakage current in scaled-down transistors where gate control is more challenging.
3Stability of the object's composition
If barrier ions are doped in the stress layer to prevent diffusion, then the electrical stability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The barrier layer is formed in advance, before the metal layer is deposited. This preliminary formation of the diffusion barrier ensures that when subsequent metal deposition and annealing steps are performed, the metal atoms are already blocked from diffusing into the stress layer. This preliminary action simplifies the overall process by preventing diffusion issues before they can occur, rather than requiring complex corrective steps later.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility and reduces leakage current by maintaining low resistivity and stable electrical properties, improving the overall performance of the transistor.
Implementation Method 1
The barrier layer can prevent atoms of the first metal element from diffusing to a bottom of the stress layer
Implementation Method 2
Because SiGe and silicon have the same crystal structure, i.e., a 'diamond' structure, and the lattice constant of SiGe is greater than the lattice constant of silicon at room temperature, a lattice mismatch thus exists between the silicon and the SiGe. Therefore, the stress layer can provide a compressive stress in the channel region, and accordingly improve the performance of the carrier mobility in the channel region of the PMOS transistor.
Implementation Method 3
An electrical contact layer can be formed using a portion of the stress layer on the barrier layer by a salicide process
Data Source
AI summary
Various embodiments provide transistors and methods for forming the same. In an exemplary method, a substrate can be provided. A gate structure can be formed on the substrate. A stress layer can be formed in the substrate on both sides of the gate structure. Barrier ions can be doped in the stress layer to form a barrier layer in the stress layer. The barrier layer can have a preset distance from a surface of the stress layer. An electrical contact layer can be formed using a portion of the stress layer on the barrier layer by a salicide process. The electrical contact layer can contain a first metal element. The first metal element can have a resistivity lower than a resistivity of a silicidation metal. The barrier layer can prevent atoms of the first metal element from diffusing to a bottom of the stress layer.