Semiconductor Dice Matching via Wafer Mapping and Die Selection
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Solution Overview
Problem
Existing methods for assembling semiconductor-based circuits using multiple dice from the same wafer often result in components with significant variations, leading to inefficiencies and increased costs due to the need for discarding non-matched dice, which affects the consistency and performance of semiconductor-based circuits.
Innovation Solution
The implementation of new electronic wafer mapping techniques and die selection methods that identify and pair dice with matching characteristics, allowing for the assembly of semiconductor-based circuits with enhanced die parity, reducing wafer-to-wafer and lot-to-lot variations by strategically positioning and bonding dice to achieve desired electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple dice from the same wafer are used to provide multiple components, then the manufacturing cost is reduced and productivity is improved, but the components exhibit significant variations in electrical parameters and characteristics
Solution Approach 1:
The patent applies preliminary action by performing wafer mapping and die selection before the actual assembly process. The system identifies and selects dice with matching characteristics in advance using electrical parameter measurements, then pairs them appropriately. This preliminary selection ensures that only dice meeting specific matching criteria are used together, resolving the contradiction between using multiple dice for productivity and maintaining component matching consistency.
2Manufacturing precision
If strict matching criteria are applied to select dice, then component consistency is improved, but the proportion of discarded dice increases and productivity decreases
Solution Approach 1:
The patent applies parameter changes by implementing a multi-level matching system that evaluates dice based on multiple electrical parameters simultaneously. The system can adjust matching criteria dynamically and use statistical methods to determine acceptable variation ranges. By optimizing the balance between matching stringency and die utilization, the system improves component consistency while minimizing discards through intelligent parameter-based selection rather than arbitrary rejection.
3Device complexity
If wafer processing is performed without advanced mapping and selection, then the manufacturing process is simpler, but significant gradients and variations in dice characteristics occur
Solution Approach 1:
The patent replaces traditional mechanical or manual die selection methods with an automated electronic wafer mapping and selection system. The system uses electrical parameter measurements and computational algorithms to identify and select matching dice, substituting intelligent automation for simpler but less precise manual processes. This resolves the contradiction by showing that the additional complexity of automated mapping and selection is necessary to achieve the required level of dice characteristic uniformity.
Data Source
AI summary
Methods and systems for achieving semiconductor-based circuits or systems having multiple components with one or more matched or similar characteristics or features are disclosed herein. In one example embodiment, a system includes a processing device that includes first, second, and third circuitry. The first circuitry is configured to generate control signals that at least indirectly cause a pick and place head mechanism to attempt to pick up and place at least some of first and second dice. The second circuitry is configured to assess whether attempts to implement one or more of first and second dice should be skipped based upon wafer map information. Further, the third circuitry is configured to determine whether a second position of a first one of the second dice is sufficiently proximate to a first position so that it would be appropriate to implement the first one of the second dice.