Variable Resistance Memory Device Joule Heat Thermal Efficiency
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high performance while maintaining low power consumption, particularly in nonvolatile memory devices that require materials with variable resistance values that persist even when current or voltage is interrupted.
Innovation Solution
A method of manufacturing a variable resistance memory device involves forming conductive patterns on a substrate, using sacrificial patterns to etch and form lower electrodes, and replacing these patterns with variable resistance materials whose resistance changes with temperature, allowing for efficient Joule's heat generation and minimal current requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional memory device structures are used, then manufacturing processes are simpler, but thermal efficiency is lower and power consumption is higher
Solution Approach 1:
The device is segmented into distinct functional layers including lower electrodes, variable resistance patterns, and upper electrodes, with each layer performing a specific function. This segmentation allows for optimized thermal management and reduced power consumption while maintaining manufacturability through standardized layering processes
Solution Approach 2:
The patent implements local quality by creating specific geometric configurations where lower electrodes have upwardly facing surfaces at different heights, and sidewall surfaces are aligned with variable resistance pattern sidewalls. This localized structural optimization enhances thermal efficiency in critical regions without requiring complete redesign of the entire device structure
2Speed
If higher current is supplied to achieve better performance, then switching speed improves, but power consumption increases
Solution Approach 1:
The patent utilizes parameter changes by employing materials with variable resistance values that change based on temperature and applied current/voltage. The variable resistance patterns transition between different resistance states, enabling fast switching speeds while maintaining low power consumption through resistance-based state changes rather than current-based switching
3Reliability
If materials with variable resistance values are used, then nonvolatile memory performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by forming sacrificial patterns that define the exact positions where variable resistance patterns will be deposited. These sacrificial patterns serve as precursors that guide subsequent material deposition, ensuring precise placement of variable resistance materials without requiring high-precision direct patterning
Solution Approach 2:
Sacrificial patterns act as intermediary elements in the manufacturing process. These temporary structures are formed first, then used to define the positions of variable resistance patterns, and finally removed or retained as part of the final structure. This intermediary approach simplifies the manufacturing process while maintaining high precision in variable resistance pattern placement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a high thermal efficiency memory cell that can be driven with a low amount of current, minimizing power consumption and enhancing thermal management, thus addressing the need for efficient and high-performance nonvolatile memory devices.
Implementation Method 1
patterns having variable resistance disposed on the lower electrodes and in contact therewith
Data Source
AI summary
A variable resistance memory device has memory cells that are operated by Joule's heat and which are highly thermally efficient. Conductive patterns are formed on a substrate; sacrificial patterns exposing a portion of the top surface of each of the conductive patterns are formed on the conductive patterns, lower electrodes are formed by etching upper portions of the conductive patterns using the sacrificial patterns as an etching mask, then mold patterns are formed on the lower electrodes and cover exposed sidewall surfaces of the sacrificial patterns, and then the sacrificial patterns are replaced with variable resistance patterns.