Asymmetric Semiconductor Layer Cross-Section for Off-Current Suppression
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Solution Overview
Problem
Current semiconductor devices with three-dimensional structures face challenges in reducing off-current while maintaining high on-current levels, particularly in vertical transistors used in nonvolatile memory devices, due to the design of the semiconductor layer cross-section which affects electron density and current flow.
Innovation Solution
The semiconductor device incorporates a semiconductor layer with a cross-sectional configuration where the width in the Y-direction is narrower at the center than at the side surfaces opposing the control electrodes, and an insulating film that covers the side surfaces, reducing off-current by minimizing the central area through which off-current flows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the semiconductor layer has a uniform cross-sectional width, then the manufacturing process is simple, but the off-current is high due to large central area
Solution Approach 1:
The semiconductor layer cross-section is designed with asymmetric width distribution, being narrower at the center than at the side surfaces. This asymmetric geometry reduces the central area where off-current flows, thereby suppressing off-current while maintaining manufacturability through standard semiconductor fabrication processes.
Solution Approach 2:
Different regions of the semiconductor layer cross-section are given different width characteristics: the side surfaces maintain larger width for sufficient on-current, while the center region is narrowed to reduce off-current. This local differentiation of geometric properties optimizes both current characteristics simultaneously.
2Object-generated harmful factors
If the central area of the semiconductor layer is reduced, then off-current is suppressed, but the on-current may be reduced
Solution Approach 1:
The semiconductor layer cross-section is designed with differentiated width across different regions: the side surfaces maintain larger width to ensure sufficient on-current flow paths, while the center region is narrowed specifically to reduce off-current. This local differentiation allows simultaneous optimization of both current characteristics.
Solution Approach 2:
By creating an asymmetric cross-sectional profile where side regions are wider than the center, the design preserves electron transport pathways at the edges for high on-current while minimizing the central area that contributes to off-current, thus resolving the trade-off between the two current types.
Data Source
AI summary
According to an embodiment, a semiconductor device includes two electrodes extending in a first direction, a semiconductor layer provided between the two electrodes, an insulating film disposed between the two electrodes. The two electrodes are arranged in a second direction intersecting the first direction. The semiconductor layer extends in a third direction orthogonal to the first direction and the second direction. The insulating film covers a side surface of the semiconductor layer opposite to one of the two electrodes. The semiconductor layer has a shape in a cross section perpendicular to the third direction such that a width in the first direction at a center of the cross section is narrower than a width, in the first direction, of the side surface.