EEPROM Memory Cell Design for Channel Length Stability
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Solution Overview
Problem
EEPROM memory cells face instability and reliability issues due to variations in channel length caused by misalignment of capacitive implant regions and gate structures, leading to short channel effects and hot carrier degradation, which limits the shrinkage of memory cells in the direction of the channel.
Innovation Solution
The solution involves an integrated circuit design where the source region of each memory cell consists only of a second capacitive implant region positioned predominantly outside the gate structure, avoiding the diffusion of the source region into the channel and maintaining a stable channel length, while the first capacitive implant region is positioned predominantly under the gate structure, allowing for a reduction in the size of the memory cells without risking hot carrier degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the channel length is reduced to shrink memory cell size, then the memory cell area is reduced, but short channel effects and hot carrier degradation occur causing instability and reliability problems
Solution Approach 1:
The source and drain regions are segmented into multiple doped zones with different doping concentrations. The source region includes a first doped zone and a second doped zone, while the drain region includes a third doped zone and a fourth doped zone. This segmentation allows independent optimization of each zone to prevent short channel effects while maintaining compact dimensions.
Solution Approach 2:
Different regions of the transistor are assigned different doping concentrations tailored to their specific functions. The first and second doped zones in the source have different concentrations, as do the third and fourth doped zones in the drain. This local quality differentiation enables the source to provide adequate doping for channel formation while the drain regions prevent hot carrier degradation, resolving the reliability issue despite reduced channel length.
2Manufacturing precision
If the capacitive implant region alignment is improved to reduce channel length variations, then the manufacturing precision is improved, but the device complexity increases
Solution Approach 1:
The source and drain regions are pre-doped with multiple doped zones before the final gate structure formation. The first doped zone of the source and the third doped zone of the drain are formed in advance with specific concentrations, creating a robust structure that compensates for potential alignment variations in subsequent processing steps, thereby reducing the need for extremely high alignment precision.
Solution Approach 2:
The doping concentration parameters are changed across different zones rather than using uniform doping. The first doped zone has a different concentration than the second doped zone, and similarly for the drain zones. This parameter variation creates a doping profile that is tolerant to alignment variations, as the graded concentrations compensate for positional deviations, reducing manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the total size of the memory cell by approximately 3% in the direction of the channel, while ensuring stability and preventing hot carrier-related degradations, thus offering an optimal compromise between size reduction and reliability.
Implementation Method 1
The capacitive implant typically has a more concentrated and shallower doping than the drain region and allows forming a capacitive structure between the drain and the floating gate in order to allow write operations.
Implementation Method 2
an implantation, in a semiconductor well, of a first capacitive implant region positioned on a drain side of the state transistor and of a second capacitive implant region positioned on a source side of the state transistor
Data Source
AI summary
The integrated circuit of a non-volatile memory of the electrically erasable and programmable type includes memory cells, each memory cell having a state transistor including a gate structure comprising a control gate and a floating gate disposed on a face of a semiconductor well, as well as a source region and a drain region in the semiconductor well. The drain region includes a first capacitive implant region positioned predominantly under the gate structure and a lightly doped region positioned predominantly outside the gate structure. The source region includes a second capacitive implant region positioned predominantly outside the gate structure, the source region not including a lightly doped region.