3D Memory Drain-Select Isolation Structures
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in effectively isolating drain-select-level structures, which affects the performance and density of memory arrays due to limitations in existing isolation techniques.
Innovation Solution
The implementation of a three-dimensional memory device with drain-select-level isolation structures featuring tubular and semi-tubular sections, where the vertical semiconductor channels have specific dopant concentrations, and the formation of these structures through a method involving alternating stacks of insulating and electrically conductive layers, along with precise etching and doping processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional isolation techniques are used in three-dimensional memory devices, then the device structure is simpler to manufacture, but the isolation efficiency and memory array density are insufficient
Solution Approach 1:
The isolation structure is segmented into multiple functional sections: a first isolation section formed in the alternating stack, a second isolation section formed in the memory stack structures, and a third isolation section formed in the substrate. This segmentation allows each section to address specific isolation needs at different levels, improving overall isolation efficiency while maintaining manageable manufacturing complexity through modular construction
Solution Approach 2:
Different isolation sections are applied at different locations with different characteristics. The first isolation section uses dielectric material in the alternating stack, the second isolation section uses doped semiconductor material in the memory stack structures, and the third isolation section is formed in the substrate. This local differentiation optimizes isolation performance for each specific region while allowing tailored manufacturing approaches
2Productivity
If existing isolation structures are used, then the manufacturing process is less complex, but the memory array density and performance are limited
Solution Approach 1:
The isolation structure implements a nested configuration where the first isolation section is embedded in the alternating stack, the second isolation section is embedded in the memory stack structures, and the third isolation section is embedded in the substrate. This nesting allows maximum utilization of available space at multiple levels, significantly increasing memory array density without requiring a proportional increase in manufacturing complexity
Solution Approach 2:
The isolation structure transitions from conventional two-dimensional planar isolation to three-dimensional vertical isolation by forming isolation sections at different elevation levels (in the substrate, in the alternating stack, and in the memory stack structures). This dimensional transformation enables higher memory array density by utilizing vertical space effectively while managing manufacturing complexity through sequential formation processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the isolation efficiency and density of memory arrays, leading to improved performance and reliability of the three-dimensional memory devices by creating effective drain-select-level isolation structures.
Implementation Method 1
implanting dopants of the first conductivity type into segments of vertical semiconductor channels within the first memory stack structures that are proximal to the drain-select-level trench
Data Source
AI summary
Electrical isolation between adjacent stripes of drain-select-level electrically conductive layers can be provided by forming a drain-select-level isolation structure between neighboring rows of memory stack structures. The drain-select-level isolation structure can partially cut through upper regions of the neighboring rows of memory stack structures. Vertical semiconductor channels of the neighboring rows of memory stack structures include a lower tubular segment and an upper semi-tubular segment that contact the drain-select-level isolation structure. Electrical current through drain select levels is limited to the semi-tubular segment of each vertical semiconductor channel. Alternatively, the drain-select-level isolation structure can be formed around the memory stack structures within the neighboring rows of memory stack structures. Ion implantation can be used to suppress conduction of electrical current through portions of vertical semiconductor channels that are proximal to the drain-select-level isolation structure.