Nonvolatile Memory Erase Voltage Delivery via GIDL
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in efficiently erasing data from three-dimensional stacked memory cells, leading to reliability issues and inefficient data erase operations.
Innovation Solution
The method involves applying an erase voltage to an erase source terminal and a higher voltage to a selection line closest to the erase source, with a lower voltage applied to a second selection line, inducing Gate Induced Drain Leakage (GIDL) to efficiently deliver the erase voltage to the memory block, and adjusting the location of GIDL based on the number of data erase operations to improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional erase methods are used in three-dimensional stacked memory cells, then the memory structure can be implemented, but the data erase operation efficiency deteriorates and reliability issues occur
Solution Approach 1:
The patent applies different voltages to different selection lines based on their position relative to the erase source terminal. The first selection line receives a first voltage, the second selection line receives a second voltage, and the third selection line receives a third voltage, creating localized voltage conditions optimized for erase operations at each position in the vertical stack.
Solution Approach 2:
The patent dynamically adjusts the voltage levels applied to different selection lines during the erase operation. By applying higher voltage to the first selection line and progressively lower voltages to subsequent selection lines, the system adapts the electric field distribution to efficiently erase data across the three-dimensional memory structure while maintaining reliability.
2Power
If erase voltage is applied to the erase source terminal, then the erase operation can be initiated, but the voltage delivery to the channel becomes inefficient
Solution Approach 1:
The patent introduces selection lines as intermediary elements between the erase source terminal and the memory block channel. These selection lines act as voltage mediators, receiving the erase voltage from the erase source terminal and progressively delivering it to different levels of the vertical memory stack, thereby improving voltage delivery efficiency.
Solution Approach 2:
The patent transitions from a conventional two-dimensional voltage delivery approach to a three-dimensional approach by utilizing vertically stacked selection lines. The erase voltage is delivered through multiple levels (first, second, and third selection lines) in the vertical dimension, enabling efficient voltage distribution throughout the three-dimensional memory structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the efficiency and reliability of data erase operations in nonvolatile memory devices by ensuring effective voltage delivery and adaptability with repeated operations.
Implementation Method 1
inducing Gate Induced Drain Leakage (GIDL) to efficiently deliver the erase voltage to the channel in the memory block
Data Source
AI summary
A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit applies an erase voltage to an erase source terminal of the memory block, and applies a first voltage to a first selection line among a plurality of selection lines in the memory block. The first voltage is higher than the erase voltage. The first selection line is disposed closest to the erase source terminal among the plurality of selection lines and is used for selecting the memory block as an erase target block.