Wordline Strapping for Non-Volatile Memory Area Reduction
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Solution Overview
Problem
The existing connection schemes for non-volatile memory technologies, such as ReRAM and MRAM, result in overly large active bitcell areas due to inefficient metal contact arrangements, which hinder efficient data access and storage.
Innovation Solution
The proposed solution involves an active array region with a wordline strap extending across the active array region, incorporating dummy bitcells in columns to provide vertical interconnections between wordlines and active bitcells, allowing for a compact and efficient layout that minimizes area disruption while enabling free expansion of the array size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If metal contacts are used to contact each individual gate of the field-effect transistors in the given row of the array with their wordline, then data access is enabled, but the active bitcell areas become overly large
Solution Approach 1:
Multiple metal contacts for individual gates are merged into a single shared metal contact that serves the entire wordline. The wordline is formed as a continuous conductive structure that electrically connects to multiple transistor gates through this single contact, eliminating the need for separate contacts for each gate and significantly reducing the area occupied by interconnect structures.
Solution Approach 2:
The shared metal contact structure serves multiple functions simultaneously: it provides electrical connection to all transistor gates in the row, acts as the wordline for data access operations, and reduces overall interconnect area. This multi-functional design replaces the conventional approach where each contact had a single dedicated function.
2Reliability
If wordline strap extends across the active array region, then wordline resistance is improved and access time is reduced, but area penalty is incurred
Solution Approach 1:
The wordline strap is positioned in a different metallization layer above the active array region rather than within the same plane as the bitcells. This vertical stacking approach allows the wordline strap to extend across the array region without occupying lateral space that would otherwise be available for active bitcells, thus reducing area penalty while still providing low-resistance connections.
Solution Approach 2:
Dummy bitcells are introduced as intermediary structures that facilitate the connection between the wordline strap and the active bitcells. These dummy structures serve as transition elements that enable the wordline strap to extend across the array region while maintaining pattern regularity and minimizing disruption to the active array layout.
Data Source
AI summary
Structures for a non-volatile memory and methods for fabricating such structures. An active array region of a memory structure includes a plurality of active bitcells and a wordline. Dummy bitcells of the memory structure are arranged in a column within the active array region. An interconnect structure includes a metallization level having a wordline strap that extends across the active array region and that is arranged over the active array region.