Single Poly-Silicon Non-Volatile Memory for CMOS Integration
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Solution Overview
Problem
Existing EEPROM technologies face integration challenges with CMOS logic processes, incur high manufacturing costs, and require time-consuming and power-intensive erasing/re-programming cycles due to their double-layer poly-silicon structure, limiting their applicability and flexibility, especially in performing byte-level operations.
Innovation Solution
A P-type channel non-volatile memory with a single poly-silicon layer structure that uses specific voltage applications for programming, reading, and erasing operations, leveraging the F-N tunneling effect and channel hot hole induced hot electron injection to selectively erase and program memory cells without affecting unselected cells, allowing for byte-level operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a double-layer poly-silicon structure is used in EEPROM, then data storage capability is improved, but integration with CMOS logic processes becomes difficult and manufacturing costs increase
Solution Approach 1:
The patent extracts the essential function of charge storage from the complex double-layer poly-silicon structure and implements it using a simpler single-layer poly-silicon structure combined with a charge trapping layer. This extraction allows the memory to maintain data storage capability while eliminating the integration difficulties and high manufacturing costs associated with the double-layer structure.
Solution Approach 2:
The patent changes the material parameters and structural configuration by replacing the double-layer poly-silicon structure with a single-layer poly-silicon structure and introducing a charge trapping layer. This parameter change enables compatibility with standard CMOS logic processes while preserving the necessary charge storage functionality.
2Reliability
If a double-layer poly-silicon structure is used in EEPROM, then charge storage is improved, but manufacturing costs increase
Solution Approach 1:
The patent employs a charge trapping layer that can be formed using standard CMOS process materials and techniques, replacing the expensive and complex double-layer poly-silicon structure. This substitution reduces manufacturing costs while maintaining adequate charge storage capability for memory operation.
3Reliability
If erasing operation is performed on a whole array or sector, then erasing completeness is improved, but time consumption and power consumption increase
Solution Approach 1:
The patent segments the erasing operation to allow selective erasure of individual memory cells or small groups of cells rather than requiring erasure of the entire array or sector. This is achieved through precise control of voltage application to specific word lines and bit lines, enabling byte-level or even cell-level erasing operations that complete faster and consume less power.
Solution Approach 2:
The patent applies partial action by erasing only the specific memory cells that need to be erased rather than performing a complete array or sector erase. This partial erasing approach reduces both time consumption and power consumption while maintaining erasing completeness for the targeted cells.
4Reliability
If erasing operation is performed on a whole array or sector, then erasing thoroughness is improved, but power consumption increases
Solution Approach 1:
The patent segments the power consumption across different memory cell groups by enabling independent control of erasing operations. Only the specific cells requiring erasure receive the high voltage necessary for the erasing process, while other cells remain in a low-power state, thereby reducing overall power consumption while maintaining erasing thoroughness for the targeted cells.
Solution Approach 2:
The patent applies partial action by limiting the erasing voltage and current to only those memory cells that require erasure, rather than applying it uniformly across the entire array or sector. This reduces the total energy consumption while ensuring thorough erasing of the necessary cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables integration with CMOS logic processes, reduces fabrication costs, improves operational efficiency, and allows for flexible, low-power byte-level operations by preventing unselected memory cells from being erased or programmed, thus enhancing the memory's speed and throughput.
Implementation Method 1
the selected memory cell is erased by an F-N tunneling effect
Implementation Method 2
programming, reading, and erasing operations, leveraging the F-N tunneling effect and channel hot hole induced hot electron injection
Data Source
AI summary
An operating method of a non-volatile memory is provided. The non-volatile memory includes plural memory cells. Each memory cell includes a charge storage structure, a gate, and a source and a drain disposed in the well on the both sides of the gate. During an erasing operation, a first voltage is applied to the source of the selected memory cell, a second voltage is applied to the gate of each selected memory cell, and a third voltage is applied to the well; and the drain of the selected memory cell is floated, so that the selected memory cell is erased. In the meantime, the fourth voltage is applied to the drain of each unselected memory cell, the fifth voltage is applied to the gate of the unselected memory cell, and the source of the unselected memory cell is floated to prevent the unselected memory cell from being erased.