TFT Array Substrate with Branch Wiring for Chamfer Reference
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Solution Overview
Problem
The existing process of cutting thin film transistor arrays from a substrate often results in peeling off of wiring and pads during the chamfer process, particularly at the outer lead bonding connections, leading to inefficiencies and defects, requiring careful labor-intensive measurement of chamfer quantities to prevent damage.
Innovation Solution
A thin film transistor array substrate with multiple chamfers is designed to include branch wiring for scale and OLB protection, which is strategically placed around the terminal face wiring to confirm chamfer quantities easily and prevent peeling of OLB pads by serving as a reference for the chamfer process, thereby reducing labor and increasing manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the chamfer process is performed to prevent defects on the cut off terminal face, then the quality of the terminal face is improved, but the wiring and pads may be peeled off from the substrate
Solution Approach 1:
The patent introduces a chamfer reference line that divides the terminal face into a first chamfering region and a second chamfering region. This segmentation allows different chamfering depths to be applied to different regions, preventing excessive chamfering that would cause wiring and pad peeling while still achieving the desired defect prevention on the terminal face.
Solution Approach 2:
The patent applies different chamfering depths to different regions of the terminal face. The first chamfering region has a greater depth than the second chamfering region, allowing localized control over the chamfering process to prevent peeling in critical areas while maintaining quality improvement in other areas.
2Reliability
If the chamfer quantity is carefully determined by frequently measuring the distance B, then the peeling of wiring and pads is prevented, but significant labor and circumspection are required for the operation
Solution Approach 1:
The chamfer reference line serves as a self-contained measurement reference that is formed directly on the substrate. It eliminates the need for external measurement tools and frequent manual measurements, allowing operators to quickly determine appropriate chamfering depth by visual reference without requiring continuous monitoring of distance B.
Solution Approach 2:
The chamfer reference line is formed on the substrate before the chamfering process begins. This preliminary action provides a pre-established measurement reference that guides the entire chamfering operation, eliminating the need for frequent intermediate measurements and reducing operational complexity.
3Manufacturing precision
If the corners of the cut off terminal face are pared away too much, then the terminal face defects are prevented, but the terminal face wiring will be peeled off from the mother substrate
Solution Approach 1:
The patent segments the terminal face into multiple chamfering regions with different depth requirements. This allows the corners to be pared away sufficiently to prevent defects while stopping before the wiring layer, thereby maintaining wiring integrity through the substrate.
Solution Approach 2:
The chamfer reference line acts as a protective guide that prevents over-chamfering. By providing a visual reference for the appropriate chamfering depth, it cushions against the harmful effect of excessive corner removal that would otherwise cause wiring peeling.
Data Source
AI summary
The present invention relates to a thin film transistor array substrate with multiple chamfers and liquid crystal display device. A wiring structure is provided on the thin film transistor array substrate with multiple chamfers which is used for producing a plurality of thin film transistor arrays from a mother substrate, said wiring structure allows the chamfer quantity to be confirmed easily in the chamfer process for cutting off the corners of the terminal face after the cutting off process for taking out the respective thin film transistor arrays, meanwhile, the OLB pads is not easy to be peeled off from the substrate, and the probability that the OLB pads are peeled off can be reduced. On the thin film transistor array substrate with multiple chamfers, on the terminal face wiring up to the boundary of the OLB pad and the cut off line, the branch wiring is configured at both sides of said wiring based on the predetermined interval as the branch wiring for scale and OLB protection, when the chamfer is performed after the thin film transistor arrays are cut off from the mother substrate, the branch wiring for scale and OLB protection is used as a scale for confirming the dimension from the terminal face of the substrate to the OLB pad, and the OLB pad is not easy to be peeled off from the substrate.