Interleaved Bit Line Memory Device for Fast Programming
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Solution Overview
Problem
Existing memory devices face challenges in achieving fast programming and read operations due to resistance-capacitance (RC) delays and capacitance between bit lines, which limit access speed and storage density.
Innovation Solution
The implementation of different sets of NAND strings with varying access speeds, where one set has high access speed and low storage density, and another set has low access speed and high storage density, by interleaving bit lines and using floating voltages to reduce inter-bit line capacitance and RC time constants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bit lines are connected to all NAND strings to increase storage density, then storage density is improved, but RC delays and inter-bit line capacitance increase causing slower access speed
Solution Approach 1:
The patent divides the bit line connections into two distinct sets: a first set of bit lines connected to a first set of NAND strings for high-speed access, and a second set of bit lines connected to a second set of NAND strings for high storage density. This segmentation allows each set to be optimized independently, resolving the contradiction between speed and density by creating specialized access paths for different operational requirements.
Solution Approach 2:
The patent applies different connection configurations to different regions of the memory device. The first set of bit lines and NAND strings is configured for fast access with minimized capacitance, while the second set is configured for maximum storage density. This local differentiation allows the system to simultaneously achieve both high speed and high density in different locations without compromise.
2Productivity
If bit lines are connected to all NAND strings to enable concurrent access, then productivity is improved, but inter-bit line capacitance increases causing RC delays
Solution Approach 1:
The patent segments the bit line infrastructure into two independent sets, allowing concurrent operation of both sets without mutual interference. The first set can perform sensing operations quickly with minimal capacitance, while the second set handles additional storage capacity. This segmentation enables the system to achieve high productivity through parallel operations while maintaining low sensing time in the first set.
Solution Approach 2:
The patent combines two different bit line configurations into a single memory device, merging the advantages of both low-capacitance fast-access design and high-density design. By interleaving these two sets, the system achieves both high productivity through concurrent access capability and low sensing time in the first set, resolving the contradiction between throughput and timing.
3Quantity of substance
If NAND strings are arranged in high-density configuration, then storage capacity is improved, but RC time constants increase reducing access speed
Solution Approach 1:
The patent segments the NAND string population into two groups with different access characteristics. The first set of NAND strings accessed through the first set of bit lines is optimized for fast access with minimized RC time constants, while the second set is optimized for maximum storage capacity. This segmentation allows the system to simultaneously provide both fast access and high storage capacity without compromise.
Solution Approach 2:
The patent implements local quality optimization by creating distinct access paths for different functional requirements. The first set of bit lines and associated NAND strings has local characteristics optimized for speed (lower capacitance, shorter paths), while the second set has local characteristics optimized for density. This local differentiation resolves the contradiction between storage capacity and access time by providing specialized paths for each requirement.
Data Source
AI summary
Techniques for fast programming and read operations for memory cells. A first set of bit lines is connected to a first set of NAND strings and is interleaved with a second set of bit lines connected to a second set of NAND strings. The first set of NAND strings can be programmed by driving a voltage on the first set of bit lines while floating a voltage on the second set of bit lines, to reduce an inter-bit line capacitance and provide a relatively high access speed and a relatively low storage density (e.g., bits per memory cell). The second set of NAND strings can be programmed by concurrently driving a voltage on the first and second sets of bit lines, to provide a relatively low access speed and a relatively high storage density.