Asymmetric FETs with Isolated Source Blocks
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Solution Overview
Problem
There is a trade-off in field effect transistors (FETs) between achieving high-quality source/drain (S/D) contacts and maintaining a small FET size, as heavy doping of S/D regions leads to undesirable short-channel effects, requiring increased gate length and chip area, which is costly and increases circuit delay.
Innovation Solution
A semiconductor structure with a doped channel region and source/drain contact regions, where the source block physically isolates the source contact region from the channel, and the drain contact region has a schottky barrier, allowing for improved short-channel voltage control without significantly increasing FET size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the S/D regions are doped more heavily to achieve better S/D contacts, then the contact quality is improved, but the depth of dopants increases leading to degraded short-channel behaviors
Solution Approach 1:
The patent applies different doping polarities to different regions: the channel region has one doping polarity while the source block has the opposite doping polarity. This local differentiation allows the source block to be heavily doped for good contact without causing the same doping depth issues in the channel, thus resolving the contradiction between contact quality and short-channel effects
Solution Approach 2:
The source/drain structure is segmented into separate source block and drain contact region, each with independent doping characteristics. The source block can be optimized for contact quality while the drain region can be optimized for short-channel control, allowing independent optimization of conflicting requirements
2Object-affected harmful factors
If the gate length is increased to separate the S/D regions further and keep the channel from being too short, then short-channel effects are reduced, but the FET size increases costing more chip area
Solution Approach 1:
The patent changes the doping polarity parameter of the source block relative to the channel region, creating an asymmetric structure that provides electrostatic control over the channel without requiring increased gate length. This allows maintaining short gate lengths for small device area while still controlling short-channel effects through the doping asymmetry
3Manufacturing precision
If the gate length is increased to reduce short-channel effects, then threshold voltage control is improved, but circuit delay increases
Solution Approach 1:
By creating local quality differences through asymmetric doping (channel with one polarity, source block with opposite polarity), the patent achieves improved threshold voltage control through enhanced electrostatic modulation without increasing gate length, thereby maintaining fast circuit speed while improving voltage control precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves a better balance between S/D contact quality and FET size, reducing short-channel effects and maintaining high circuit speed with minimal voltage loss, while allowing for a shallow drain structure that controls threshold voltage effectively.
Implementation Method 1
a semiconductor source block doped with a second doping polarity and in direct physical contact with the semiconductor channel region
Implementation Method 2
the drain contact region has a schottky barrier, allowing for improved short-channel voltage control
Implementation Method 3
field effect transistors (FETs)... a gate stack in direct physical contact with the semiconductor channel region
Implementation Method 4
increases the depth of dopants of the S/D regions and leads to degraded short-channel behaviors, such as increased Drain-Induced Barrier Lowering
Data Source
AI summary
A semiconductor structure and a method for forming the same. The structure includes (a) a semiconductor channel region, (b) a semiconductor source block in direct physical contact with the semiconductor channel region; (c) a source contact region in direct physical contact with the semiconductor source block, wherein the source contact region comprises a first electrically conducting material, and wherein the semiconductor source block physically isolates the source contact region from the semiconductor channel region, and (d) a drain contact region in direct physical contact with the semiconductor channel region, wherein the semiconductor channel region is disposed between the semiconductor source block and the drain contact region, and wherein the drain contact region comprises a second electrically conducting material; and (e) a gate stack in direct physical contact with the semiconductor channel region.