Asymmetric FinFET Gate Offset Reduces Parasitic Capacitance
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Solution Overview
Problem
The increasing complexity and parasitic capacitance in CMOS devices, particularly in RF circuits, lead to significant time delays and signal degradation due to smaller process geometries and the Miller effect, impacting the performance and accuracy of high-density integrated circuits.
Innovation Solution
The solution involves forming a semiconductor device with a buried channel region doped away from the surface of the fin structure and extending the distance between the gate structure and source/drain features to minimize parasitic capacitance, thereby reducing time delays and signal degradation. This is achieved through specific doping processes and structural arrangements, such as forming a hard mask layer with asymmetrical openings and recesses to position source/drain features optimally relative to the gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If process geometries are reduced to increase functional density, then the number of interconnected devices per chip area increases, but parasitic capacitance increases causing time delays and signal degradation
Solution Approach 1:
The gate structure is intentionally offset from the central axis of the fin structure, creating an asymmetric configuration where the gate is positioned closer to one side of the fin. This asymmetry reduces the overlap area between the gate and source/drain regions, thereby reducing parasitic capacitance while maintaining compact device geometry for high functional density
Solution Approach 2:
The doping concentration in the fin structure is varied spatially, with higher doping concentrations near the gate interface and lower concentrations in other regions. This local variation optimizes carrier concentration to reduce parasitic capacitance effects while maintaining device performance in the critical regions
2Area of stationary object
If source/drain features are positioned closer to gate structure to reduce device area, then device footprint decreases, but parasitic capacitance increases causing signal degradation
Solution Approach 1:
The gate structure is offset from the fin centerline, creating asymmetric spacing between the gate and source/drain regions. This allows the device to maintain a compact footprint while the asymmetric geometry reduces the overlapping area that generates parasitic capacitance, resolving the contradiction between small size and low parasitic effects
3Speed
If operating frequency is increased to improve circuit performance, then signal processing speed improves, but time delays from parasitic capacitance increase causing signal degradation
Solution Approach 1:
The harmful parasitic capacitance effect is extracted and reduced by offsetting the gate structure from the fin centerline. This separation reduces the capacitive coupling between gate and source/drain regions, minimizing the time delays that would otherwise limit high-frequency operation, thereby enabling improved operating frequencies
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, enhancing the speed and accuracy of the semiconductor device, allowing for higher operating frequencies and maintaining high interconnect density with reduced delay variation, as demonstrated by semiconductor devices operating at frequencies higher than 350 GHz.
Implementation Method 1
forming a buried channel region doped away from the surface of the fin structure
Data Source
AI summary
A method for forming a semiconductor device is provided. The method includes forming a gate structure over a fin structure. The method includes forming a hard mask layer over the gate structure. The hard mask layer has a first opening spaced apart from a first side of the gate structure by a first distance and a second opening spaced apart from a second side of the gate structure by a second distance that is different from the first distance. The method also includes removing the fin structure not covered by the hard mask layer. The method further includes forming a first source/drain feature in the fin structure and filling the first opening of the hard mask layer. The method further includes forming a second source/drain feature in the fin structure and filling the second opening of the hard mask layer.