Asymmetric FinFET Source/Drain Structures for Etch-Controlled Performance
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Solution Overview
Problem
The semiconductor industry faces challenges in accurately controlling deposition and patterning processes during the fabrication of FinFET devices, particularly in advanced process nodes, which can lead to deteriorated electrical performance due to inaccurate source/drain structure formation.
Innovation Solution
The formation of asymmetric source/drain structures with different dimensions and profiles is achieved by using etchants with high selectivity to trim and pattern these structures at varying active regions, allowing for flexible adjustment of electrical performance through the use of n-type and p-type regions with distinct epi-material growth rates and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional symmetric source/drain structures are used in FinFET fabrication, then manufacturing process is simpler, but electrical performance deteriorates due to inaccurate control of deposition and patterning processes
Solution Approach 1:
The patent applies asymmetry by forming source/drain structures with different heights on opposite sides of the gate structure. The first source/drain structure has a first height and the second source/drain structure has a second height that is different from the first height. This asymmetric configuration compensates for process variations and improves electrical performance by optimizing carrier transport in each direction independently.
Solution Approach 2:
The patent implements local quality by creating different source/drain structures at different locations. The first source/drain structure on one side of the gate has different dimensions and properties than the second source/drain structure on the other side. This allows optimization of electrical characteristics locally at each source/drain region rather than using a uniform structure throughout.
2Reliability
If asymmetric source/drain structures with different heights are formed, then electrical performance is improved through optimized carrier transport, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies segmentation by dividing the source/drain formation process into separate stages. First, a common source/drain structure is formed across the substrate, then selective removal or addition processes are applied to create the asymmetric heights. This segmentation allows independent control of each source/drain structure's final dimensions while using standardized process modules.
Solution Approach 2:
The patent uses preliminary action by forming a uniform source/drain structure before creating the asymmetric configuration. The initial symmetric structure provides a stable foundation, and subsequent selective processing steps (such as selective etching or selective deposition) create the final asymmetric heights. This preliminary uniform structure simplifies the overall manufacturing control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical performance of semiconductor devices by optimizing source/drain structures, improving electron mobility and reducing contact resistance, thereby addressing the limitations of traditional fabrication methods.
Implementation Method 1
etching a first source/drain structure in a first active region at a first etching rate and etching a second source/drain structure in a second active region at a second etching rate by an etching gas mixture, the first etching rate being faster than the second etching rate
Implementation Method 2
the etching gas mixture including a sulfur containing passivation gas, the sulfur containing passivation gas forming a protective layer on the second source/drain structure
Data Source
AI summary
The present disclosure provides semiconductor devices with asymmetric source/drain structures. In one example, a semiconductor device includes a first group of source/drain structures on a first group of fin structures on a substrate, a second group of source/drain structures on a second group of fin structures on the substrate, and a first gate structure and a second gate structure over the first and the second group of fin structures, respectively, the first and second groups of source/drain structures being proximate the first and second gate structures, respectively, wherein the first group of source/drain structures on the first group of fin structures has a first source/drain structure having a first vertical height different from a second vertical height of a second source/drain structure of the second group of source/drain structures on the second group of fin structures.