Semiconductor/Solid-State Device Manufacturing TRIZ Cases

A lowered spacer beside the SDB helps FinFET fabrication improve channel and threshold control while reducing DIBL and short channel effects.

A movable support block and rotating vacuum holder bend flexible display panels while protecting wiring lines and preserving bend curvature.

Solid reactant vaporization with pressure control keeps reaction gas concentration constant while shrinking gas supplier volume.

Pre-staging containers on a mounting structure cuts waiting time and keeps substrate transfer moving even when the transport structure is busy.

A low-viscosity photocurable resin forms a wafer edge protective film that blocks metal adhesion and withstands exposure and etching.

Sequential ion implantation with annealing shapes doped regions more precisely, improving on-state resistance control in power semiconductors.

Patterned trenches and MELO enable kerfless epitaxial layer extraction and substrate reuse, cutting WBG substrate cost and defects.

Localized laser heating through absorptive and reflective metal layers forms ohmic contacts on high-power diodes without damaging nearby layers.

Pre-storing low- and high-vapor-pressure reactive gases stabilizes simultaneous gas delivery and improves film formation uniformity.

Floating body segments in trench field plate MOSFET termination suppress triple-point fields, raising breakdown voltage and widening process margin.

Electron beam, UV or plasma treatment enables low-temperature silicon nitrogenous films with low oxygen content, high refractive index, and trench fill.

Polyaminoamide leveling agents improve copper feature filling, reducing voids, mounding, and CMP removal in microvia and TSV plating.

Detachable covers with matched vias let one injection mold fit power modules with different pin locations, cutting mold change cost and delay.

An NH-group adsorption layer suppresses reaction by-product adhesion during substrate film deposition, improving uniformity in high-aspect-ratio features.

A divided pad layout and shorter word-line connection path raise memory cell density while improving signal speed and yield.

A side doping layer expands bit line contact to the semiconductor channel, improving conductivity, gate control, and integration in GAA memory structures.

Two etching gases with different depth profiles widen uneven recess openings and enable void-free silicon film filling in semiconductor processing.

A staggered laser path at intersecting dicing lines prevents chip-corner chipping during wafer division and preserves device chip quality.

Thicker gate dielectric corners in a recessed MOSFET stabilize threshold voltage and current slope by blocking undesired substrate current.

Laser annealing grows vertically elongated channel grains to improve current flow and channel thickness control with lower thermal budget.

A two-stage nitriding sequence improves SiC gate oxide uniformity while suppressing interface carbon, nitrogen loss, and leak current.

A high-reflectance, rough-surface source gas nozzle stays cooler in the reaction tube, reducing organic decomposition and film thickness variation.

A patterned outgas prevention layer retains noise-reducing material during anneal, cutting MOSFET flicker noise without added cost.

Cuts the wafer’s peripheral margin to dress the blade, avoiding dummy wafers and reducing replacement steps during chip division.

Self-aligned double patterning with directional spacer etching improves sub-28 nm line spacing while reducing lithography complexity and cost.

Protective hard mask spacers and gap filling cut etch exposure in multi-patterning, improving pattern transfer and smaller feature formation.

A vapor chamber built into the display backplane spreads CPU heat to the housing while supporting modular laptop reuse and easier disassembly.

A selectively grown cap layer protects the FinFET fin during gate dielectric formation, preserving fin width, integrity, and carrier mobility.

An NH-group adsorption layer is cycled before source and reactive gases to limit by-product adhesion and improve film uniformity.

A flowable polymer protects the bottom metal liner during selective PVD, enabling seam-free, void-free filling of sub-20 nm features.

A tuned phenolic resin underlayer improves adhesion, film formability, and dry-etch resistance for precise staircase patterning in 3D NAND.

Bottom-side supercritical fluid supply reduces wafer pattern collapse and drying defects by controlling pressure and flow in the chamber.

A low-molecular-weight resist underlayer composition fills fine patterns without voids while reducing sublimates and improving wet etch resistance.

Removing surface oxide before depositing a thin SiC interface layer cuts carbon-related charge trapping and improves gate insulation reliability.

Controller-based precoat thickness limits prevent lift pin binding and substrate support displacement during semiconductor deposition.

Purge gas flow and reflector cooling keep isolated chamber components near set-points, improving deposition uniformity and uptime.

A side-mounted interface with posture turning and relay regions lets batch tool length change without reworking wafer transport paths.

An inboard-outboard chamber layout with an added load-lock expands process chamber connectivity to cut handling time and raise throughput.

A non-reducing promoting agent boosts organic-ligand modifier adsorption, improving metal film continuity and limiting inhibiting by-products.

Segmented mandrels create short and long trenches in one patterning flow, enabling mixed-length semiconductor features with lower process complexity and cost.

A cap-protected implanted diffusion region enables ohmic contact in nitride semiconductors while limiting anneal-induced gate leakage.

A metal and high-κ stack forms the transistor dipole region without spike anneal, cutting thermal budget and oxide-thickness penalties.

A rotating laser beam patterns wafer streets before plasma etching, reducing chipping, cracking, and cleaning while improving die yield.

Laser-formed modified layers let wafer chamfers break away cleanly during thinning, reducing contamination, sharp edges, and chip chipping.

Alternating pipe heating and cooling suppresses oxygen-driven oxidation, preventing burnout and contamination during substrate processing.

A thin encapsulated semiconductor film segments into oxygen-trapping agglomerates, enabling strong bonded interfaces with high vertical conduction.

Back-side radiation sensing through a transmissive channel enables precise substrate temperature and coating control during one-sided heating and opposite-side treatment.

Printed-and-erased dummy features keep only pattern overlaps, improving IC etch uniformity, CD consistency, and routing efficiency.

Patterned holes in a 2D material layer let upper and lower layers couple directly, improving adhesion and process stability in semiconductor stacks.