Double Patterning With Erasable Dummies for Uniform IC Etching
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Solution Overview
Problem
Conventional patterning techniques face challenges in achieving consistent critical dimension (CD) control and etch uniformity across varying pattern densities in integrated circuit (IC) manufacturing, leading to issues with transistor and interconnect routing efficiency and performance.
Innovation Solution
The 'AND' dual patterning method involves creating overlaid patterns on a substrate, where non-overlapping patterns are printed and then erased to allow for precise etch control and feature formation, enabling sharp corners and uniform CDs by retaining only overlapping pattern intersections, thus optimizing etch control and reducing unnecessary chip area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional dummification is used to improve etch control, then etch uniformity is improved, but chip area is occupied and routing efficiency is degraded
Solution Approach 1:
The dummification pattern is segmented into multiple layers: a first pattern layer providing etch control signal, and a second pattern layer providing additional etch uniformity. This segmentation allows each layer to serve its specific function without interfering with routing, as the patterns are distributed across different lithographic layers rather than occupying the same physical space in a single layer
Solution Approach 2:
The solution moves from two-dimensional planar dummification to three-dimensional multi-layer patterning. By stacking patterns in the vertical dimension (different lithographic layers), the patent achieves etch control without consuming horizontal chip area, thereby maintaining routing efficiency while improving etch uniformity
2Adaptability or versatility
If wide pattern density is used to accommodate mixed IC interconnect routing, then design flexibility is improved, but etch control signal is insufficient leading to CD variation
Solution Approach 1:
The patent pre-establishes a pattern layer specifically designed to provide etch control signal before the actual interconnect routing pattern is formed. This preliminary pattern layer is optimized for etch uniformity and can be removed or modified afterward, allowing wide pattern density flexibility in the final design without compromising etch control
Data Source
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Figure 3A~3B
AI summary
A method for manufacturing integrated circuit (IC) devices includes forming first and second mask patterns with overlapping and non-overlapping features. Non-overlapping features may be removed before etching a target material layer. A third mask pattern may be formed from the overlapping features and used to etch a target material layer. The third mask pattern may be employed to make regular arrays of substantially rectangular structures. An IC device may include an IC die, an array of structures on a layer of the IC die, and multiple groups of parallel stripes of indentations or depressions in the layer. The structures may each include a transistor and a capacitor.