Vertical Channel Memory Cell Layout for Faster Word Line Routing
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing integration density and improving operation speed and production yield as they are scaled down, particularly in effectively utilizing vertical channel transistors for enhanced electrical characteristics and resistance.
Innovation Solution
A semiconductor device design that includes a substrate with first and second transistors, a bit line connected to the first transistor, a channel layer, a gate insulating layer, a word line, a landing pad connected to the channel layer, and a connection pad connected to the word line and second transistor, with a division structure separating the landing and connection pads, and a conductive connection pattern to reduce the electrical conduction path length between the word line and the second transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the device is scaled down to increase integration density, then the integration density is improved, but the operation speed and production yield deteriorate
Solution Approach 1:
The patent transitions from planar transistors to vertical channel transistors, utilizing the vertical dimension to increase integration density while maintaining electrical performance. The vertical channel structure allows current to flow vertically through the channel layer, enabling higher density without sacrificing operation speed.
Solution Approach 2:
The device is segmented into distinct functional regions including vertical channel transistors, drift regions, and specialized pad structures. This segmentation allows optimization of each region for its specific function while maintaining overall device performance at scaled dimensions.
2Quantity of substance
If the device is scaled down to increase integration density, then the integration density is improved, but the production yield deteriorates
Solution Approach 1:
The patent incorporates a division structure with an intervening portion between the landing pad and connection pad that extends into the drift region. This structure provides electrical isolation and prevents short circuits, cushioning against manufacturing variations and defects that could otherwise reduce production yield.
Solution Approach 2:
The intervening portion of the division structure acts as an intermediary element that electrically isolates the landing pad from the connection pad and drift region. This mediator prevents harmful electrical interactions while maintaining the compact scaled-down structure.
3Speed
If the electrical conduction path length is reduced to improve signal transmission speed, then the operation speed is improved, but the device layout complexity increases
Solution Approach 1:
The vertical channel transistor structure utilizes the vertical dimension to create direct electrical pathways from the channel layer to the bit line and word line through the drift region. This vertical arrangement shortens the conduction path length compared to planar structures while the systematic layout of vertical channels maintains manufacturing simplicity.
Data Source
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AI summary
A semiconductor device includes a substrate, a first transistor and a second transistor on the substrate, a bit line electrically connected to the first transistor, a channel layer on the bit line, a gate insulating layer on the channel layer, a word line on the gate insulating layer, a landing pad electrically connected to the channel layer, a connection pad electrically connected to the word line and the second transistor, and a division structure separating the landing pad from the connection pad. The division structure includes an intervening portion between the landing pad and the connection pad.