Vertical Transistor Grain Alignment for Precise Channel Thickness
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Solution Overview
Problem
Current transistors in memory cells face challenges in achieving optimal current flow and operational characteristics due to limitations in channel region crystal grain size and alignment, which affect the precision of vertical thickness control and overall performance.
Innovation Solution
The development of transistors with a channel region comprising vertically-elongated crystal grains directly against both top and bottom source/drain regions, along with specific annealing methods such as laser annealing, to enhance crystal grain size and alignment, thereby improving current flow and operational characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistors are used with standard crystal grain size in the channel region, then manufacturing is simpler, but current flow and operational characteristics are suboptimal
Solution Approach 1:
The patent applies parameter changes by modifying the crystal grain size parameter in the channel region to be larger than in conventional transistors. This is achieved through specific annealing processes that control the crystallization parameters, resulting in improved current flow and operational characteristics while managing the increased manufacturing complexity through controlled process parameters.
Solution Approach 2:
The patent employs preliminary action by performing annealing processes before final transistor formation to pre-establish the desired crystal grain structure in the channel region. This preliminary crystallization step ensures optimal grain size and orientation are achieved before subsequent fabrication steps, improving final device performance.
2Manufacturing precision
If the channel region has small crystal grain size, then manufacturing precision is easier to achieve, but vertical thickness control precision deteriorates
Solution Approach 1:
The patent utilizes parameter changes in the annealing process to control crystal grain growth. By adjusting temperature, time, and atmospheric parameters during annealing, the patent achieves precise control over vertical thickness while promoting larger crystal grain formation, thereby resolving the contradiction between manufacturing precision and operational ease.
3Reliability
If extensive annealing is performed to increase crystal grain size, then operational characteristics improve, but thermal budget increases
Solution Approach 1:
The patent applies preliminary action by performing the annealing process at an early stage in the fabrication sequence, before other high-temperature steps. This allows the crystal grains to grow to optimal size while the overall thermal budget is still being accumulated, reducing the need for additional extensive annealing later in the process.
Solution Approach 2:
The patent exploits phase transitions during controlled annealing to promote crystal grain growth. By carefully managing the thermal cycle through specific heating and cooling rates, the patent achieves significant grain size increase with moderate thermal input, improving operational characteristics without excessive thermal budget consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in increased average crystal grain size in the channel region, enabling more precise control of vertical thicknesses and optimizing operational attributes of the transistor, while reducing the thermal budget during fabrication.
Implementation Method 1
In at least two time-spaced laser annealing steps, at least two of the bottom, top, and middle materials are laser annealed to melt and then crystallize the at least two of the bottom, top, and middle materials to be crystalline
Implementation Method 2
laser annealed to melt and then crystallize the at least two of the bottom, top, and middle materials to be crystalline
Data Source
AI summary
A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.