Integrated Dipole Region in Transistors Without Spike Anneal
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Solution Overview
Problem
Conventional dipole engineering techniques face challenges in achieving desired dipole effects in transistors due to high thermal budgets and equivalent oxide thickness penalties, particularly when scaling down device sizes, as they require spike anneal processes that can oxidize underlying silicon layers.
Innovation Solution
The integration of a dipole region in electronic devices, comprising an interfacial layer, a metal film free or substantially free of non-metal atoms, and a high-κ dielectric layer, which forms a dipole region without the need for spike anneal, allowing metal atoms to diffuse and tune the thickness without oxidation penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spike anneal is used to achieve dipole effect, then desired dipole effect is achieved, but thermal budget increases and equivalent oxide thickness penalty occurs
Solution Approach 1:
The patent extracts the harmful spike anneal process from the dipole formation sequence, achieving dipole effect through sequential deposition of metal and high-k dielectric layers without requiring high-temperature annealing. This removes the thermal budget penalty while maintaining the desired dipole effect.
Solution Approach 2:
The patent performs preliminary deposition of the metal layer followed by high-k dielectric layer in a controlled sequence, establishing the dipole structure before any thermal processing. This preliminary formation of the dipole stack avoids subsequent high-temperature annealing that would cause oxidation and EOT penalty.
2Reliability
If spike anneal is used to achieve dipole effect, then desired dipole effect is achieved, but equivalent oxide thickness penalty occurs due to oxidation
Solution Approach 1:
The patent converts the potential harm of oxidation into a benefit by using the controlled oxidation state during deposition to form the dipole structure, then avoiding further oxidation through low-temperature processing. The metal layer is deposited in a controlled environment that prevents excessive oxidation, maintaining precise EOT control while achieving the dipole effect.
Solution Approach 2:
The patent changes the processing parameters from high-temperature spike anneal to low-temperature sequential deposition, controlling the oxidation state during deposition rather than through post-deposition annealing. This parameter change maintains precise EOT control while achieving the desired dipole effect.
3Reliability
If conventional dipole engineering is used, then dipole effect can be achieved, but process complexity increases due to multiple steps
Solution Approach 1:
The patent merges the dipole formation process with the existing gate stack deposition sequence, integrating the metal and high-k dielectric layer deposition into the standard CMOS fabrication flow. This consolidation reduces process complexity by eliminating separate spike anneal steps and integrating dipole formation into the existing deposition sequence.
Solution Approach 2:
The patent creates a universal dipole formation approach that works across different transistor types and threshold voltage requirements by using standard deposition techniques that can be applied throughout the fabrication process. This multi-functional approach eliminates the need for specialized spike anneal equipment and processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces thermal budgets and maintains desired dipole effects without the need for annealing, simplifying integration and potentially reducing integration costs while minimizing oxidation, thus addressing the limitations of conventional methods.
Implementation Method 1
allowing metal atoms to diffuse and tune the thickness without oxidation penalties
Data Source
AI summary
Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-κ dielectric layer on the metal film. In some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-κ dielectric layer on the interfacial layer, and a metal film on the high-κ dielectric layer. In some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-κ dielectric layer.