FinFET SDB Spacer Structure for Channel and Threshold Control
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Solution Overview
Problem
Current FinFET fabrication methods face challenges in integrating single diffusion break (SDB) structures and metal gate fabrication, leading to inefficiencies in controlling the channel region and threshold voltage of fin-shaped transistors.
Innovation Solution
A method involving the formation of fin-shaped structures on a substrate, followed by the creation of trenches and dielectric layer filling to form SDB and gate isolation structures, with specific steps including forming a gate layer, removing parts to create trenches, and filling these with a dielectric layer, while also forming epitaxial layers and hard masks to achieve precise control over the transistor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional FinFET fabrication methods are used to form SDB structures, then the integration process becomes complex and inefficient, but the channel region control and threshold voltage control remain insufficient
Solution Approach 1:
The patent divides the fin-shaped structure into multiple segments by forming trenches between adjacent fins. This segmentation approach allows independent control of each fin segment, enabling precise channel region control and threshold voltage adjustment while simplifying the integration process for SDB structures
Solution Approach 2:
The patent applies local quality by forming SDB structures selectively in specific regions between fins rather than uniformly across all fins. This allows different channel lengths and threshold voltages in different locations, improving control precision without increasing overall process complexity
2Productivity
If the gate length is reduced to scale down transistor size, then the transistor density increases, but the drain-induced barrier lowering effect and short channel effect worsen
Solution Approach 1:
The patent transitions from planar gate control to three-dimensional FinFET structure with vertical fins, adding a vertical dimension to the channel. This dimensional change allows maintaining effective channel control even when horizontal gate length is reduced, thereby improving transistor density while mitigating short channel effects
Solution Approach 2:
The patent introduces可调性 (adjustability) in channel length by selectively removing parts of fins to form trenches, creating variable channel lengths within the same device. This dynamic adjustment capability allows optimization of channel length to reduce DIBL and short channel effects while maintaining high transistor density
3Reliability
If the overlapping area between gate and fin-shaped structure is increased to improve channel control, then the DIBL effect is reduced, but the device area increases
Solution Approach 1:
By segmenting fins into controlled sections with trenches, the patent achieves effective gate control over each segment without requiring increased overall gate-fin overlapping area. The segmented structure allows precise control with compact footprint
4Ease of manufacture
If SDB structure and metal gate fabrication are integrated using current methods, then the process steps are numerous and complex, but the manufacturing efficiency remains low
Solution Approach 1:
The patent merges the SDB structure formation and metal gate fabrication into a unified process flow. By forming trenches and SDB structures before metal gate deposition, multiple functions are achieved in integrated steps, simplifying the manufacturing process and improving efficiency
Data Source
AI summary
A semiconductor device includes a gate structure on a substrate, a single diffusion break (SDB) structure adjacent to the gate structure, a first spacer adjacent to the gate structure, a second spacer adjacent to the SDB structure, a source/drain region between the first spacer and the second spacer, an interlayer dielectric (ILD) layer around the gate structure and the SDB structure, and a contact plug in the ILD layer and on the source/drain region. Preferably, a top surface of the second spacer is lower than a top surface of the first spacer.