Semiconductor Hard Mask Spacer Patterning for Etch Damage Control
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving sufficient resolution in multi-patterning techniques for advanced process nodes, leading to increased etching exposure and damage to mask layers, which affects the uniformity and accuracy of patterned features in integrated circuits.
Innovation Solution
A method involving the formation of a hard mask with spacers and trenches, where a patterned layer and mask layer are used to reduce etching exposure and damage, allowing for a more uniform topography and controllable height, and utilizing a gap-filling material to enhance etch selectivity and patterning performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional photolithographic exposures are used to achieve sufficient resolution in multi-patterning, then feature resolution is improved, but etching exposure time increases causing damage to mask layers
Solution Approach 1:
The patent divides the patterning process into multiple sequential steps: forming mandrels, depositing spacers, removing mandrels, and repeating the process. This segmentation allows each step to be optimized independently, reducing cumulative etching damage while achieving the desired feature resolution through progressive pattern refinement.
Solution Approach 2:
The patent performs preliminary actions by forming protective spacer layers and hard mask layers before the final etching process. These pre-formed structures serve as protective barriers that reduce etching damage to the mask layers during subsequent processing steps.
2Manufacturing precision
If extended etching exposure is used to transfer patterns through multiple layers, then pattern transfer completeness is improved, but damage to mask layers and underlying structures increases
Solution Approach 1:
The patent introduces intermediary hard mask layers and spacer structures that act as mediators between the photolithographic pattern and the underlying layers to be etched. These intermediary structures absorb etching damage and protect the primary mask layers, enabling complete pattern transfer while maintaining mask integrity.
Solution Approach 2:
The patent changes material parameters by selecting hard mask materials with high etch selectivity and appropriate spacer materials that provide both structural support and damage resistance. These parameter changes enable the etching process to proceed through multiple layers without compromising mask layer integrity.
3Area of moving object
If repeated photolithographic exposures are performed to define features at advanced nodes, then integration density is improved, but cumulative etching damage reduces manufacturing precision
Solution Approach 1:
The patent segments the multi-patterning process into distinct stages with intermediate processing steps, including spacer formation and mandrel removal. This segmentation resets the damage accumulation between pattern definition steps, maintaining pattern uniformity while achieving high integration density through repeated exposures.
Solution Approach 2:
The spacer structures formed in each patterning cycle serve a dual purpose: they define the next pattern generation while simultaneously protecting underlying structures from etching damage. This self-service function reduces cumulative damage and maintains manufacturing precision across multiple patterning cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces damage to mask layers and improves patterning performance by minimizing etching exposure, enabling better pattern transfer to underlying layers and achieving smaller features without defects, while being compatible with existing semiconductor processes and cost-effective.
Implementation Method 1
An etching process is then used to pattern the mask layer to form first features (e.g., spacers) in a first (x-axis) direction along sidewalls of the patterned layer and form trenches in the dielectric layer
Implementation Method 2
depositing a first hard mask layer and a first dielectric layer over a substrate; forming a patterned layer over the first dielectric layer; forming a second hard mask layer over the patterned layer
Data Source
AI summary
A method for manufacturing a semiconductor device includes depositing a first hard mask layer and a first dielectric layer over a substrate, forming a patterned layer over the first dielectric layer, forming a second hard mask layer over the patterned layer, patterning the second hard mask layer to remove first horizontal portions of the second hard mask layer and leave second portions of the second hard mask layer along sidewalls of the patterned layer, etching a trench in the first dielectric layer using the second portions of the second hard mask layer and the patterned layer as an etching mask, depositing a first gap-filling material in the trench and patterning the first hard mask layer using the first gap-filling material, the patterned layer, and the second portions of the second hard mask layer as a mask.