Semiconductor Bonding Interface with Agglomerates for Vertical Conduction

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Solution Overview

Problem

Existing methods for forming semiconductor structures with direct contact between a high-quality semiconductor layer and a lower-quality support substrate often result in suboptimal bonding interfaces, leading to issues with vertical electrical conduction and mechanical strength due to the formation of amorphous layers and native oxide layers.

Innovation Solution

A method involving the deposition of a thin film of a semiconductor material different from the layer and substrate, followed by annealing to create regions of direct contact and agglomerates at the interface, which traps oxygen and enhances bonding without generating amorphous layers, thereby improving electrical and mechanical properties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If direct bonding is performed between the useful layer and support substrate, then mechanical strength and electrical conduction are improved, but amorphous layers form at the interface which degrade electrical conductivity

Engineering Contradiction:
Improvemechanical strengthVSAvoidelectrical conductivity
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The patent segments the bonding interface into discrete nanoscale contact spots rather than a continuous amorphous layer. By forming isolated direct contact regions between crystalline domains, the interface maintains mechanical strength while preserving electrical conductivity pathways through the crystalline regions, avoiding the formation of continuous amorphous layers that would degrade conductivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by creating heterogeneous interface structures with different properties in different regions. Direct contact spots provide strong mechanical bonding and good electrical conductivity, while intervening regions may have different characteristics. This spatial variation in interface quality allows simultaneous optimization of both mechanical strength and electrical conductivity.

Inventive Principle:
Principle #3Local quality

2Strength

If molecular adhesion bonding is used to bond the useful layer and support substrate, then bonding is achieved, but native oxide layers prevent direct contact and reduce interface quality

Engineering Contradiction:
Improvebonding strengthVSAvoidinterface quality
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by performing surface activation treatments (such as plasma treatment, chemical etching, or mechanical polishing) before bonding to remove native oxide layers and create fresh, reactive surfaces. This preliminary surface preparation ensures that when bonding occurs, direct contact between crystalline regions can be established without oxide interference, thereby achieving both strong bonding and high interface quality.

Inventive Principle:
Principle #10Preliminary action

3Strength

If argon bombardment is used to activate surfaces for bonding, then covalent bonds form at the interface with high bonding energy, but an amorphous layer is generated which adversely impacts vertical electrical conduction

Engineering Contradiction:
Improvebonding energyVSAvoidvertical electrical conduction
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The patent applies partial action by using controlled, moderate argon bombardment or alternative activation methods that provide sufficient surface activation for covalent bonding without excessive energy input that would create extensive amorphous layers. By optimizing the dosage and duration of surface activation, the patent achieves adequate bonding energy while minimizing amorphous layer formation, thus preserving electrical conduction properties.

Inventive Principle:
Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in a semiconductor structure with enhanced vertical electrical conductivity and mechanical strength, achieving resistivity levels comparable to a massive substrate while maintaining high-quality crystalline integrity.

Implementation Method 1

the agglomerates comprising a semiconductor material, other than the semiconductor material(s) of the layer and the support substrate, and having a thickness, along an axis normal to the main plane, less than or equal to 250 nm; the regions of direct contact and the agglomerates being adjacent in the main plane

Methodology Applied
Scientific EffectOxygen trapping: Absorption (physical)

Implementation Method 2

A well-known thin-film transfer solution is the Smart Cut process, based on light ion implantation and direct bonding assembly at a bonding interface

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 3

e) annealing the intermediate structure at a temperature greater than or equal to a critical temperature, so as to cause the segmentation of the encapsulated film

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 4

Some state-of-the-art solutions propose to achieve a bond, by molecular adhesion, semiconductor on semiconductor, between the useful layer and the support substrate

Methodology Applied
Scientific EffectMolecular adhesion: Adhesive

Data Source

PatentEP4264659B1Method for producing a semiconductor structure comprising an interface region including agglomerates
Publication Date: 2025.01.01 SOITEC SA
  • EP4264659B1 patent drawingFigure 1~2b
  • EP4264659B1 patent drawingFigure 2c~2e
  • EP4264659B1 patent drawingFigure 3a~3c

AI summary

The invention relates to a method for producing a semiconductor structure comprising the following steps: a) providing a working layer made of a semiconductor material; b) providing a carrier substrate made of a semiconductor material; c) depositing a film composed of a semiconductor material different from that or those of the working layer and of the carrier substrate, having a thickness of less than 50 nm, on the free face to be joined of the working layer and/or on the free face to be joined of the carrier substrate; d) forming an intermediate structure, comprising directly joining, along a bonding interface extending along a main plane, the free faces to be joined of the working layer and of the carrier substrate, respectively, the intermediate structure comprising an encapsulated film originating from the one or more films deposited in step c); e) annealing the intermediate structure at a temperature higher than or equal to a critical temperature, so as to bring about segmentation of the encapsulated film and form the semiconductor structure comprising an interface region between the working layer and the carrier substrate, said interface region comprising: - regions of direct contact between the working layer and the carrier substrate; and - agglomerates comprising the semiconductor material of the film, and having a thickness, along an axis normal to the main plane, of less than or equal to 250 nm; the regions of direct contact and the agglomerates being adjacent in the main plane.