Nitride Semiconductor Contact Structure for Low Gate Leakage

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Solution Overview

Problem

The manufacturing method for nitride semiconductor devices faces issues with surface decomposition during activation annealing, leading to increased gate leakage due to crystal structure and stoichiometry collapse, as well as oxidation and carbon/silicon pile-up, which affects the crystallinity and electrical properties.

Innovation Solution

A nitride semiconductor device structure with a damaged region created by ion implantation and a diffusion region formed through high-temperature annealing, where an ohmic electrode is in contact with the diffusion region, reducing contact resistance and gate leakage by maintaining crystallinity and stoichiometry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If activation annealing is performed after ion implantation, then impurity activation and diffusion are achieved, but surface decomposition occurs causing crystal structure collapse and increased gate leakage

Engineering Contradiction:

Improvegate leakageVSAvoidcrystal structure

Core Design Contradiction:

ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent applies preliminary action by forming a protective cap layer (third nitride semiconductor layer) before performing activation annealing. This cap layer prevents surface decomposition and maintains crystal structure stability during the high-temperature annealing process, while still allowing impurity activation and diffusion to occur in the underlying layers.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The cap layer acts as an intermediary protective barrier between the annealing environment and the nitride semiconductor layer. It mediates the thermal stress and prevents direct interaction between the high-temperature annealing process and the semiconductor surface, thereby preventing crystal structure collapse while enabling impurity activation.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If high-temperature activation annealing is performed, then impurity diffusion is enhanced, but oxidation and carbon/silicon pile-up occur increasing gate leakage

Engineering Contradiction:

Improveimpurity diffusionVSAvoidoxidation and carbon/silicon pile-up

Core Design Contradiction:

Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The patent employs an inert atmosphere (nitrogen or vacuum environment) during activation annealing to prevent oxidation of the nitride semiconductor surface. This inert environment allows high-temperature annealing to proceed without introducing oxygen-related contaminants, while still enabling effective impurity diffusion.

Inventive Principle:

Principle #39Inert atmosphere (Inert environment)

Solution Approach 2:

The cap layer is formed in advance to prevent oxidation and carbon/silicon pile-up before they can occur during annealing. This preliminary protective measure enables the annealing process to proceed at high temperatures without generating harmful surface contaminants.

Inventive Principle:

Principle #10Preliminary action

3Ease of manufacture

If room temperature ion implantation is performed, then implantation process is simplified, but epitaxial growth layer becomes amorphous with poor crystallinity

Engineering Contradiction:

Improveion implantation processVSAvoidcrystallinity

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent changes the temperature parameter during ion implantation from room temperature to high temperature (700-1100°C). This parameter change maintains the simplicity of the implantation process while preventing amorphization of the epitaxial growth layer, thereby preserving crystallinity. The high temperature enables the implantation to occur without damaging the crystal structure.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces contact resistance, on-resistance, and gate leakage, while maintaining high crystallinity, thereby enhancing the performance of nitride semiconductor devices by increasing drain current and reducing surface leakage.

Implementation Method 1

a damaged region in which an n-type impurity is selectively added by ion implantation

Methodology Applied

Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

a diffusion region in which the n-type impurity is diffused

Methodology Applied

Scientific EffectDiffusion: Diffusion

Data Source

PatentUS20250006798A1Nitride semiconductor device and manufacturing method therefor

Publication Date: 2025.01.02 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD

AI summary

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer provided over the substrate; a second nitride semiconductor layer that is on the first nitride semiconductor layer and includes a band gap larger than a band gap of the first nitride semiconductor layer; and a third nitride semiconductor layer that is on the second nitride semiconductor layer and includes a band gap larger than the band gap of the first nitride semiconductor layer. The second nitride semiconductor layer includes a damaged region in which an n-type impurity is selectively added by ion implantation. A diffusion region in which the n-type impurity is diffused is present in a vicinity of the damaged region. The nitride semiconductor device further includes: an ohmic electrode provided above the damaged region. The ohmic electrode is in ohmic contact with the diffusion region.