Asymmetric GAA Nanosheet Gate Layout for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing gate-all-around transistors face challenges in achieving high density and efficient scaling due to limitations in channel layer coverage by the gate electrode, leading to increased parasitic capacitance and reduced operating speed.
Innovation Solution
The semiconductor device incorporates a gate electrode design where the source/drain layer protrudes beyond the gate electrode ends, with specific distances and alignments to reduce parasitic capacitance and improve operating speed, utilizing asymmetric gate structures for nanosheet channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode is designed to fully surround the channel layers for complete coverage, then the channel coverage is improved, but the parasitic capacitance increases and operating speed decreases
Solution Approach 1:
The gate electrode is designed with an asymmetric configuration where it does not completely surround the channel layers. Specifically, the gate electrode extends along the channel length but deliberately leaves one end of the channel layer uncovered. This asymmetric design reduces the parasitic capacitance between the gate electrode and channel layer while maintaining sufficient gate control over the majority of the channel, thereby improving operating speed without completely sacrificing channel coverage control.
2Reliability
If the gate electrode extends beyond the channel layers to provide complete coverage, then the channel coverage is improved, but the device complexity and manufacturing precision requirements increase
Solution Approach 1:
The asymmetric gate electrode design deliberately avoids the need for perfect symmetry and complete coverage. By designing the gate to extend only partially along the channel length, the manufacturing process does not require precise alignment to cover the entire channel perimeter. This reduces the manufacturing precision requirements while still achieving effective gate control over the active channel region.
3Reliability
If the source/drain layer is positioned to contact all channel layers uniformly, then the electrical characteristics are improved, but the device complexity increases
Solution Approach 1:
The source/drain layer is positioned to contact the channel layers at specific locations rather than uniformly along the entire channel length. The asymmetric gate configuration allows the source/drain layer to be optimally positioned at regions where electrical contact is most effective, while leaving other regions without contact. This local optimization approach improves electrical characteristics without requiring a uniformly complex structure throughout the entire device.
Data Source
AI summary
A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other, and having first side surfaces and second side surfaces opposing each other in a first direction, a gate electrode surrounding the channel layers and having a first end portion and a second end portion, opposing each other in the first direction, and a source/drain layer on a first side of the gate electrode and in contact with the channel layers, a portion of the source/drain layer protruding further than the first end portion of the gate electrode in the first direction, wherein a first distance from the first end portion of the gate electrode to the first side surfaces of the channel layers is shorter than a second distance from the second end portion of the gate electrode to the second side surfaces of the channel layers.