Asymmetric Gate Contact Widths for Semiconductor Integration
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Solution Overview
Problem
Semiconductor devices face challenges in securing a stable contact area between gate contacts and gate electrodes while minimizing the occurrence of short circuits between gate and source/drain contacts as the pitch size decreases, requiring effective capacitance reduction and electrical stability.
Innovation Solution
The semiconductor device design includes active patterns with specific spacing and orientation, gate electrodes extending in particular directions, and gate contacts with varying widths to ensure contact area security and reduce short circuits, utilizing nanosheets and source/drain regions with protruding contact portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch size is decreased for high integration, then the device density and integration level are improved, but the contact area between gate contact and gate electrode is reduced and the risk of short circuit between gate contact and source/drain contact increases
Solution Approach 1:
The gate contact is designed with asymmetric dimensions where the first dimension (width) is greater than the second dimension (length), creating an optimized contact geometry that maximizes contact area while maintaining proper spacing from source/drain contacts. This asymmetric design allows the gate contact to securely contact the gate electrode without increasing the overall pitch size, thus resolving the contradiction between high integration and contact reliability.
Solution Approach 2:
The contact structure employs local quality optimization by giving different dimensional characteristics to different parts of the gate contact. The larger first dimension provides enhanced contact area with the gate electrode at the critical contact location, while the overall compact structure maintains small pitch size for high integration. This localized dimensional optimization ensures reliable contact without compromising device density.
2Reliability
If the contact area between gate contact and gate electrode is increased to ensure stable contact, then the contact reliability is improved, but the distance to source/drain contact decreases increasing short circuit risk
Solution Approach 1:
The gate contact uses asymmetric dimensions where the first dimension (greater than the second dimension) is oriented to maximize contact area with the gate electrode while the overall shape maintains appropriate spacing from source/drain contacts. This asymmetric geometry allows enhanced contact reliability without reducing the safety margin against short circuits.
Solution Approach 2:
The solution addresses the contact area vs. spacing contradiction by utilizing dimensional optimization - the gate contact has a larger dimension in one direction for contact area while maintaining compactness in the perpendicular direction to preserve spacing from source/drain contacts. This dimensional strategy enables both reliable contact and short circuit prevention.
Data Source
AI summary
A semiconductor device includes a first active pattern that extends in a first horizontal direction, a second active pattern which extends in the first horizontal direction, and is spaced apart from the first active pattern by a first distance in a second horizontal direction, a third active pattern which extends in the first horizontal direction, and is spaced apart from the second active pattern by a second distance greater than the first distance in the second horizontal direction, a first gate electrode which extends in the second horizontal direction on the first to third active patterns, a second gate electrode which extends in the second horizontal direction on the first and second active patterns, and is spaced apart from the first gate electrode in the first horizontal direction, a first gate contact and a second gate contact which extends in the second horizontal direction on the second gate electrode.