Nanoinformatics TRIZ Cases

A slanted fin tunnel field-effect transistor uses polar GaN heterojunctions to generate internal electric fields.

Diketopyrrolopyrrole copolymers enhance energy conversion efficiency and stability despite synthesis complexity.

Segmenting the device into distinct regions allows concurrent parallel signal processing and learning without mutual interference.

Shadow deposition creates complex nanoimprint mold patterns, resolving the trade-off between manufacturing precision and fabrication throughput.

A PFPE-based reactive copolymer resist composition enables defect-free sub-100 nm nanoimprinting.

Photo-lithographic patterning defines vertical OFET electrodes, resolving manufacturing precision limits inherent in shadow mask alignment methods.

A carbon-based storage element paired with a steering diode enables rewritable multilevel memory cells.

Flowable dielectric fills cavities under channel layers, preventing SiGe intermixing and maintaining STI oxide robustness.

Flocculating carbon nanotubes with surfactants prevents aggregation and waste while ensuring uniform dispersion on the substrate.

Merging processing chambers eliminates substrate transfer contamination while reducing total cycle time for cladding layer formation.

An offset drain structure in a separate plane enables high voltage operation without component damage.

Alternating semiconductor and non-semiconductor monolayers lower conductivity effective mass to reduce on-resistance in high-performance DMOS transistors.

Matching template and substrate stiffness while controlling separation forces and velocities resolves strain mismatch defects like sheared or torn features.

A semiconductor layered structure uses MBE epitaxial growth to form quantum dots within a matrix region.

Gate and spacer structures mask semiconductor layers during patterning, ensuring uniform dopant profiles that improve transistor reliability.

Solid phase diffusion places dopants into fin channel regions for gate all-around transistors.

A semiconductor device uses asymmetric gate contact widths to secure stable electrical connections between gate electrodes and source drain regions.

Silicon migration thins nanowires in silicon-on-insulator field-effect transistors, reducing line edge roughness and improving charge transport.

An intermediary carbon film blocks metal atom migration into the dielectric, reducing leakage current while maintaining integration density.

Sidewall spacers split the gate stack to define control and select gates, eliminating separate mask steps that limit integration density.

Continuous epitaxial source and drain growth in gate-all-around transistors establishes compressive strain within silicon channel layers.

A quantum dot field-effect transistor fabrication method removes surface ligands using chemical exposure to modify the device interface.

Optimized bithiopheneimide polymers resolve carrier mobility and film morphology trade-offs to boost fill factors above 70%.

Self-organizing InGaN nanowires form quantum dots without foreign metal catalysts.

Dual dielectric layers in the gate stack reduce interface state generation and parasitic capacitance, lowering off-state leakage.

Heating treatment at 110 to 170°C relaxes film stress in Mo/Si multilayer reflective films, reducing substrate deformation during EUV lithography.

Selective dummy dielectric deposition compensates for loading effects, maintaining consistent gate lengths in vertical transistors.

Insulating nanoparticle layers concentrate current to lower programming energy and improve resistance uniformity in phase change memory devices.

Selective oxidation creates germanium nanowires with controlled strain to enhance carrier mobility while managing process complexity.

A doped dielectric layer creates a bandgap in graphene double-layers, resolving power loss and instability issues inherent in conventional pn-junctions.

A fabrication technique forms upward-pointing p-i-n diodes with optimized doping profiles to ensure consistent electrical conductivity across large arrays.

A semiconductor device structure integrates a protective layer extending into a cap layer over a gate stack to define transistor channels.

A detector uses separate illumination sources to form light intensity poles in orthogonal directions for single-system detection.

A pattern transfer apparatus evenly distributes usage across multiple template regions to maintain balanced wear.

Integrated spacer processes control inner spacer thickness and position, reducing source/drain recess variability in nanosheet transistors.

High-pressure gas-phase passivation creates a protection layer that reduces side wall etch and maintains device structure integrity.

ZnO-based electrodes form conducting filaments to reduce driving voltage and enhance charge injection efficiency.

A three-dimensional electric element arranges nonlinear units in a spatial configuration to build compact machine learning systems.

A silicon tunneling field effect transistor positions a source region underneath a gate dielectric to enable band-to-band tunneling.

Copper conductive elements replace aluminum or tungsten in resistivity changing memory devices to enable low temperature fabrication.

A soft mold patterns thin films with hydrophilic polymer resin, eliminating photoresist costs and fabrication time.

A cantilever-based probe tip assembly enables lateral and vertical movement for precise tracking during data storage operations.

An indirectly induced tunnel emitter structure introduces carrier concentration in the source region of a core element to enable band-to-band tunneling.

A scope observes substrate and mold marks to detect displacement, enabling real-time correction of alignment errors.

A memory device uses a double helix biopolymer layer containing distributed metal nanoparticles to store data via conductivity states.

Asymmetric mold geometry blocks resin extrusion to the base, eliminating burrs and etching steps.

A CFET-based 8T SRAM bit cell stacks NMOS and PMOS devices vertically to create a dual-port memory structure with shared gates.

A carbon nanotube tunneling transistor uses a molybdenum disulfide film to achieve n-type doping.

Ion implantation creates an internal conductive layer in quartz substrates, eliminating complex metal deposition and removal steps.