Non-planar III-V Device Gate Stack with Dual Dielectric Layers
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Solution Overview
Problem
Non-planar semiconductor devices with group III-V material active regions face challenges in reducing junction leakage and improving carrier mobility due to interface state generation and high parasitic capacitance caused by high-k gate dielectrics, which limits their performance in high-speed and low-power applications.
Innovation Solution
The introduction of a dual oxide/passivation layer with a low dielectric constant outer oxide layer in the gate stack reduces interface state generation and parasitic capacitance, enhancing carrier mobility and reducing off-state leakage by acting as both a gate spacer and part of the gate stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high-k gate dielectric is used in the gate stack, then gate capacitance is increased, but interface state generation and parasitic capacitance increase causing junction leakage
Solution Approach 1:
The gate dielectric stack is segmented into multiple layers with different dielectric constants. The first dielectric layer has a dielectric constant of 3.9-7.0 and the second dielectric layer has a dielectric constant greater than 8. This segmentation allows the lower-k first layer to reduce parasitic capacitance and interface states while the higher-k second layer maintains gate capacitance for high drive current.
Solution Approach 2:
The gate dielectric stack uses a composite structure combining two different dielectric materials. The first dielectric layer (lower-k) and second dielectric layer (higher-k) are deposited in sequence to create a composite structure that balances the competing requirements of low parasitic capacitance and high gate capacitance.
2Productivity
If device dimensions are scaled down to increase density, then capacity is increased, but junction leakage increases
Solution Approach 1:
Different regions of the gate stack have different dielectric properties optimized for their specific functions. The first dielectric layer closer to the channel has lower-k to minimize parasitic effects at the critical interface, while the second dielectric layer provides higher-k for sufficient gate control. This local quality differentiation addresses leakage issues in scaled devices.
3Reliability
If group III-V material is used for high carrier mobility, then drive current performance is improved, but off-state leakage increases due to interface states
Solution Approach 1:
The first dielectric layer with lower dielectric constant acts as an intermediary between the high-k second dielectric layer and the group III-V channel. This intermediary layer reduces interface state generation and parasitic capacitance that would otherwise occur at the high-k/III-V interface, thereby reducing off-state leakage while maintaining the benefits of high carrier mobility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively decreases interface trap density, lowers parasitic capacitance, and improves mobility in the channel region, leading to better performance in terms of reduced leakage and enhanced RF performance in non-planar semiconductor devices.
Implementation Method 1
The gate stack includes a first dielectric layer conformal with the trench and disposed on outer portions, but not an inner portion, of the channel region. A second, different, dielectric layer is conformal with the first dielectric layer and disposed on the inner portion of the channel region.
Implementation Method 2
The introduction of a dual oxide/passivation layer with a low dielectric constant outer oxide layer in the gate stack reduces interface state generation and parasitic capacitance, enhancing carrier mobility
Data Source
Figure 1A~1B
Figure 2~3
Figure 4
AI summary
Non-planar semiconductor devices having group III-V material active regions With multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body With a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.